XC3S5000-5FGG676C Datasheet, PDF (43/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Each BUFGMUX element, shown in Figure 24, is a 2-to-1 multiplexer that can receive signals from any of the four following
sources:
• One of the four Global Clock inputs on the same side of the die—top or bottom—as the BUFGMUX element in use.
• Any of four nearby horizontal Double lines.
• Any of four outputs from the DCM in the right-hand quadrant that is on the same side of the die as the BUFGMUX
element in use.
• Any of four outputs from the DCM in the left-hand quadrant that is on the same side of the die as the BUFGMUX
element in use.
The multiplexer select line, S, chooses which of the two inputs, I0 or I1, drives the BUFGMUX’s output signal, O, as
described in Table 25. The switching from one clock to the other is glitchless, and done in such a way that the output High
and Low times are never shorter than the shortest High or Low time of either input clock.
Table 25: BUFGMUX Select Mechanism
S Input
O Output
0
I0 Input
1
I1 Input
The two clock inputs can be asynchronous with regard to each other, and the S input can change at any time, except for a
short setup time prior to the rising edge of the presently selected clock (I0 or I1). Violating this setup time requirement can
result in an undefined runt pulse output.
The BUFG clock buffer primitive drives a single clock signal onto the clock network and is essentially the same element as
a BUFGMUX, just without the clock select mechanism. Similarly, the BUFGCE primitive creates an enabled clock buffer
using the BUFGMUX select mechanism.
Each BUFGMUX buffers incoming clock signals to two possible destinations:
• The vertical spine belonging to the same side of the die—top or bottom—as the BUFGMUX element in use. The two
spines—top and bottom—each comprise four vertical clock lines, each running from one of the BUFGMUX elements
on the same side towards the center of the die. At the center of the die, clock signals reach the eight-line horizontal
spine, which spans the width of the die. In turn, the horizontal spine branches out into a subsidiary clock interconnect
that accesses the CLBs.
• The clock input of either DCM on the same side of the die—top or bottom—as the BUFGMUX element in use.
Use either a BUFGMUX element or a BUFG (Global Clock Buffer) element to place a Global input in the design. For the
purpose of minimizing the dynamic power dissipation of the clock network, the Xilinx development software automatically
disables all clock line segments that a design does not use.
A global clock line ideally drives clock inputs on the various clocked elements within the FPGA, such as CLB or IOB flip-flops
or block RAMs. A global clock line also optionally drives combinatorial inputs. However, doing so provides additional loading
on the clock line that might also affect clock jitter. Ideally, drive combinatorial inputs using the signal that also drives the input
to the BUFGMUX or BUFG element.
For more details, refer to the chapter entitled “Using Global Clock Resources” in UG331.
DS099 (v3.1) June 27, 2013
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Product Specification
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