XC3S5000-5FGG676C Datasheet, PDF (94/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 59: Switching Characteristics for the DLL
Symbol
Description
Output Frequency Ranges
CLKOUT_FREQ_1X_LF
Frequency for the CLK0,
CLK90, CLK180, and CLK270
outputs
CLKOUT_FREQ_1X_HF
Frequency for the CLK0 and
CLK180 outputs
CLKOUT_FREQ_2X_LF⁽³⁾
Frequency for the CLK2X and
CLK2X180 outputs
CLKOUT_FREQ_DV_LF
CLKOUT_FREQ_DV_HF
Frequency for the CLKDV
output
Output Clock Jitter⁽⁴⁾
CLKOUT_PER_JITT_0
Period jitter at the CLK0
output
CLKOUT_PER_JITT_90
Period jitter at the CLK90
output
CLKOUT_PER_JITT_180
Period jitter at the CLK180
output
CLKOUT_PER_JITT_270
Period jitter at the CLK270
output
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and
CLK2X180 outputs
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV
output when performing
integer division
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV
output when performing
non-integer division
Duty Cycle
CLKOUT_DUTY_CYCLE_DLL⁽⁵⁾
Duty cycle variation for the
CLK0, CLK90, CLK180,
CLK270, CLK2X, CLK2X180,
and CLKDV outputs
Phase Alignment
CLKIN_CLKFB_PHASE
CLKOUT_PHASE
Phase offset between the
CLKIN and CLKFB inputs
Phase offset between any two
DLL outputs (except CLK2X
and CLK0)
Phase offset between the
CLK2X and CLK0 outputs
Frequency Mode /
FCLKIN Range
Low
High
Low
Low
High
All
All
All
Device
Speed Grade
-5
-4
Units
Min Max Min Max
All
18 167 18 167 MHz
48 280 48 280 MHz
36 334 36 334 MHz
1.125 110 1.125 110 MHz
3 185 3 185 MHz
All
– ±100 – ±100 ps
– ±150 – ±150 ps
– ±150 – ±150 ps
– ±150 – ±150 ps
– ±200 – ±200 ps
– ±150 – ±150 ps
– ±300 – ±300 ps
XC3S50
– ±150 – ±150 ps
XC3S200 – ±150 – ±150 ps
XC3S400 – ±250 – ±250 ps
XC3S1000 – ±400 – ±400 ps
XC3S1500 – ±400 – ±400 ps
XC3S2000 – ±400 – ±400 ps
XC3S4000 – ±400 – ±400 ps
XC3S5000 – ±400 – ±400 ps
All
– ±150 – ±150 ps
– ±140 – ±140 ps
– ±250 – ±250 ps
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
94