XC3S5000-5FGG676C Datasheet, PDF (116/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
The 1% precision impedance-matching resistor attached to the VRN_# pin controls the pull-down impedance of NMOS
transistor in the input or output buffer. Consequently, the VRN_# pin must connect to VCCO. The ‘N’ character in “VRN”
indicates that this pin controls the I/O buffer’s NMOS transistor impedance. The VRN_# pin is only used for split termination.
Each VRN or VRP reference input requires its own resistor. A single resistor cannot be shared between VRN or VRP pins
associated with different banks.
During configuration, these pins behave exactly like user-I/O pins. The associated DCI behavior is not active or valid until
after configuration completes.
Also see Digitally Controlled Impedance (DCI), page 16.
DCI Termination Types
If the I/O in an I/O bank do not use the DCI feature, then no external resistors are required and both the VRP_# and VRN_#
pins are available for user I/O, as shown in section [a] of Figure 42.
If the I/O standards within the associated I/O bank require single termination—such as GTL_DCI, GTLP_DCI, or
HSTL_III_DCI—then only the VRP_# signal connects to a 1% precision impedance-matching resistor, as shown in section
[b] of Figure 42. A resistor is not required for the VRN_# pin.
Finally, if the I/O standards with the associated I/O bank require split termination—such as HSTL_I_DCI, SSTL2_I_DCI,
SSTL2_II_DCI, or LVDS_25_DCI and LVDSEXT_25_DCI receivers—then both the VRP_# and VRN_# pins connect to
separate 1% precision impedance-matching resistors, as shown in section [c] of Figure 42. Neither pin is available for user
I/O.
X-Ref Target - Figure 42
One of eight
I/O Banks
User I/O
User I/O
One of eight
I/O Banks
VRN
VRP
R_REF (1%)
One of eight
I/O Banks
VRN
VRP
VCCO
R_REF (1%)
R_REF (1%)
(a) No termination
(b) Single termination
(c) Split termination
Figure 42: DCI Termination Types
DS099-4_03_091910
GCLK: Global Clock Buffer Inputs or General-Purpose I/O Pins
These pins are user-I/O pins unless they specifically connect to one of the eight low-skew global clock buffers on the device,
specified using the IBUFG primitive.
There are eight GCLK pins per device and two each appear in the top-edge banks, Bank 0 and 1, and the bottom-edge
banks, Banks 4 and 5. See Figure 40 for a picture of bank labeling.
During configuration, these pins behave exactly like user-I/O pins.
Also see Global Clock Network, page 42.
CONFIG: Dedicated Configuration Pins
The dedicated configuration pins control the configuration process and are not available as user-I/O pins. Every package
has seven dedicated configuration pins. All CONFIG-type pins are powered by the +2.5V VCCAUX supply.
Also see Configuration, page 46.
DS099 (v3.1) June 27, 2013
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Product Specification
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