XC3S5000-5FGG676C Datasheet, PDF (111/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 70: Spartan-3 FPGA Pin Definitions (Cont’d)
Pin Name
TDI
Input
Direction
TMS
Input
TDO
Output
VCCO: I/O bank output voltage supply pins
VCCO_#
Supply
VCCAUX: Auxiliary voltage supply pins
VCCAUX
Supply
VCCINT: Internal core voltage supply pins
VCCINT
Supply
GND: Ground supply pins
GND
Supply
N.C.: Unconnected package pins
N.C.
Description
JTAG Test Data Input:
TDI is the serial data input for all JTAG instruction and data registers. This
pin has an internal pull-up resistor to VCCAUX during configuration.
JTAG Test Mode Select:
The serial TMS input controls the operation of the JTAG port. This pin has
an internal pull-up resistor to VCCAUX during configuration.
JTAG Test Data Output:
TDO is the serial data output for all JTAG instruction and data registers.
This pin has an internal pull-up resistor to VCCAUX during configuration.
Power Supply for Output Buffer Drivers (per bank):
These pins power the output drivers within a specific I/O bank.
Power Supply for Auxiliary Circuits:
+2.5V power pins for auxiliary circuits, including the Digital Clock
Managers (DCMs), the dedicated configuration pins (CONFIG), and the
dedicated JTAG pins. All VCCAUX pins must be connected.
Power Supply for Internal Core Logic:
+1.2V power pins for the internal logic. All pins must be connected.
Ground:
Ground pins, which are connected to the power supply’s return path. All
pins must be connected.
Unconnected Package Pin:
These package pins are unconnected.
Notes:
1. All unused inputs and bidirectional pins must be tied either High or Low. For unused enable inputs, apply the level that disables the
associated function. One common approach is to activate internal pull-up or pull-down resistors. An alternative approach is to externally
connect the pin to either VCCO or GND.
2. All outputs are of the totem-pole type — i.e., they can drive High as well as Low logic levels — except for the cases where “Open Drain” is
indicated. The latter can only drive a Low logic level and require a pull-up resistor to produce a High logic level.
Detailed, Functional Pin Descriptions
I/O Type: Unrestricted, General-purpose I/O Pins
After configuration, I/O-type pins are inputs, outputs, bidirectional I/O, three-state outputs, open-drain outputs, or
open-source outputs, as defined in the application
Pins labeled "IO" support all SelectIO™ interface signal standards except differential standards. A given device at most only
has a few of these pins.
A majority of the general-purpose I/O pins are labeled in the format “IO_Lxxy_#”. These pins support all SelectIO signal
standards, including the differential standards such as LVDS, ULVDS, BLVDS, RSDS, or LDT.
For additional information, see IOBs, page 10
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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