XC3S5000-5FGG676C Datasheet, PDF (206/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 103: FG676 Package Pinout (Cont’d)
Bank
XC3S1000
Pin Name
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
N/A VCCINT
VCC CCLK
AUX
VCC DONE
AUX
VCC HSWAP_EN
AUX
VCC M0
AUX
VCC M1
AUX
VCC M2
AUX
VCC PROG_B
AUX
VCC TCK
AUX
VCC TDI
AUX
VCC TDO
AUX
VCC TMS
AUX
XC3S1500
Pin Name
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
XC3S2000
Pin Name
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
XC3S4000
Pin Name
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
XC3S5000
Pin Name
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
FG676 Pin
Number
Type
U17 VCCINT
U18 VCCINT
V9
VCCINT
V10 VCCINT
V17 VCCINT
V18 VCCINT
W8
VCCINT
W19 VCCINT
AD26 CONFIG
AC24 CONFIG
C2
CONFIG
AE3 CONFIG
AC3 CONFIG
AF3 CONFIG
D3
CONFIG
B24
JTAG
C1
JTAG
D24
JTAG
A24
JTAG
Notes:
1. XC3S1500 balls D25 and F25 are not VREF pins although they are designated as such. If a design uses an IOSTANDARD requiring VREF in bank
2 then apply the workaround in Answer Record 20519.
2. XC3S4000 is pin compatible with XC3S2000 but uses alternate differential pair labeling on six package balls (H20, H21, H22, H23, H24, J21).
3. XC3S5000 is pin compatible with XC3S4000 but uses alternate differential pair functionality on fifteen package balls (A3, A8, B8, B18, C4, C8, C18,
D8, D18, E8, E18, H23, H24, AB9, and AC9).
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
206