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| XC3S5000-5FGG676C Datasheet, PDF (82/272 Pages) Xilinx, Inc – Introduction and Ordering Information | |||
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 48: Test Methods for Timing Measurement at I/Os (Contâd)
Signal Standard
(IOSTANDARD)
HSTL_III_18
HSTL_III_DCI_18
LVCMOS12
LVCMOS15
LVDCI_15
LVDCI_DV2_15
HSLVDCI_15
LVCMOS18
LVDCI_18
LVDCI_DV2_18
HSLVDCI_18
LVCMOS25
LVDCI_25
LVDCI_DV2_25
HSLVDCI_25
LVCMOS33
LVDCI_33
LVDCI_DV2_33
HSLVDCI_33
LVTTL
PCI33_3
Rising
Falling
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL2_I
SSTL2_I_DCI
SSTL2_II
SSTL2_II_DCI
Differential
LDT_25 (ULVDS_25)
LVDS_25
LVDS_25_DCI
BLVDS_25
LVDSEXT_25
LVDSEXT_25_DCI
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_HSTL_II_18_DCI
VREF (V)
1.1
-
-
Inputs
VL (V)
VREF â 0.5
0
0
VH (V)
VREF + 0.5
1.2
1.5
-
0
1.8
-
0
2.5
-
0
3.3
-
-
0.9
0.9
1.25
1.25
0
Note 3
VREF â 0.5
VREF â 0.5
VREF â 0.75
VREF â 0.75
3.3
Note 3
VREF + 0.5
VREF + 0.5
VREF + 0.75
VREF + 0.75
-
VICM â 0.125 VICM + 0.125
-
VICM â 0.125 VICM + 0.125
-
VICM â 0.125 VICM + 0.125
-
VICM â 0.125 VICM + 0.125
-
VICM â 0.3
VICM + 0.3
-
VICM â 0.1
VICM + 0.1
-
VICM â 0.5
VICM + 0.5
Outputs
RT (Ω)
50
VT (V)
1.8
1M
0
1M
0
1M
0
1M
0
1M
0
1M
0
25
0
25
3.3
50
0.9
50
0.9
50
1.25
25
1.25
50
1.25
60
0.6
50
1.2
N/A
N/A
1M
0
50
1.2
N/A
N/A
1M
0
50
1.2
50
1.8
Inputs and
Outputs
VM (V)
VREF
0.6
0.75
0.9
1.25
1.65
1.4
0.94
2.03
VREF
VREF
VREF
VREF
VICM
VICM
VICM
VICM
VICM
VICM
VICM
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
82
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