XC3S5000-5FGG676C Datasheet, PDF (207/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 104 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S1000 in the
FG676 package. Similarly, Table 105 shows how the available user-I/O pins are distributed between the eight I/O banks for
the XC3S1500 in the FG676 package. Finally, Table 106 shows the same information for the XC3S2000, XC3S4000, and
XC3S5000 in the FG676 package.
Table 104: User I/Os Per Bank for XC3S1000 in FG676 Package
Edge
I/O
Bank
Maximum I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
49
40
0
2
5
Top
1
50
41
0
2
5
2
48
41
0
2
5
Right
3
48
41
0
2
5
4
50
35
6
2
5
Bottom
5
50
35
6
2
5
6
48
41
0
2
5
Left
7
48
41
0
2
5
GCLK
2
2
0
0
2
2
0
0
Table 105: User I/Os Per Bank for XC3S1500 in FG676 Package
Edge
I/O
Bank
Maximum I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
62
52
0
2
6
Top
1
61
51
0
2
6
2
60
52
0
2
6
Right
3
60
52
0
2
6
4
63
47
6
2
6
Bottom
5
61
45
6
2
6
6
60
52
0
2
6
Left
7
60
52
0
2
6
GCLK
2
2
0
0
2
2
0
0
Table 106: User I/Os Per Bank for XC3S2000, XC3S4000, and XC3S5000 in FG676 Package
Edge
I/O Bank Maximum I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
62
52
0
2
6
Top
1
61
51
0
2
6
2
61
53
0
2
6
Right
3
60
52
0
2
6
4
63
47
6
2
6
Bottom
5
61
45
6
2
6
6
61
53
0
2
6
Left
7
60
52
0
2
6
GCLK
2
2
0
0
2
2
0
0
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
207