XC3S5000-5FGG676C Datasheet, PDF (112/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Differential Pair Labeling
A pin supports differential standards if the pin is labeled in the format “Lxxy_#”. The pin name suffix has the following
significance. Figure 40 provides a specific example showing a differential input to and a differential output from Bank 2.
• ‘L’ indicates differential capability.
• "xx" is a two-digit integer, unique for each bank, that identifies a differential pin-pair.
• ‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the inverted. These two pins form one differential pin-pair.
• ‘#’ is an integer, 0 through 7, indicating the associated I/O bank.
If unused, these pins are in a high impedance state. The Bitstream generator option UnusedPin enables a pull-up or
pull-down resistor on all unused I/O pins.
Behavior from Power-On through End of Configuration
During the configuration process, all pins that are not actively involved in the configuration process are in a high-impedance
state. The CONFIG- and JTAG-type pins have an internal pull-up resistor to VCCAUX during configuration. For all other I/O
pins, the HSWAP_EN input determines whether or not pull-up resistors are activated during configuration. HSWAP_EN = 0
enables the pull-up resistors. HSWAP_EN = 1 disables the pull-up resistors allowing the pins to float, which is the desired
state for hot-swap applications.
X-Ref Target - Figure 40
Bank 0
Bank 5
Bank 1
IO_L38P_2
Pair Number
Bank Number
IO_L38N_2
IO_L39P_2
Positive Polarity,
True Receiver
IO_L39N_2
Bank 4
Negative Polarity,
Inverted Receiver
DS099-4_01_091710
Figure 40: Differential Pair Labelling
DUAL Type: Dual-Purpose Configuration and I/O Pins
These pins serve dual purposes. The user-I/O pins are temporarily borrowed during the configuration process to load
configuration data into the FPGA. After configuration, these pins are then usually available as a user I/O in the application.
If a pin is not applicable to the specific configuration mode—controlled by the mode select pins M2, M1, and M0—then the
pin behaves as an I/O-type pin.
There are 12 dual-purpose configuration pins on every package, six of which are part of I/O Bank 4, the other six part of I/O
Bank 5. Only a few of the pins in Bank 4 are used in the Serial configuration modes.
See Pin Behavior During Configuration, page 122.
Serial Configuration Modes
This section describes the dual-purpose pins used during either Master or Slave Serial mode. See Table 75 for Mode Select
pin settings required for Serial modes. All such pins are in Bank 4 and powered by VCCO_4.
In both the Master and Slave Serial modes, DIN is the serial configuration data input. The D1-D7 inputs are unused in serial
mode and behave like general-purpose I/O pins.
In all the cases, the configuration data is synchronized to the rising edge of the CCLK clock signal.
The DIN, DOUT, and INIT_B pins can be retained in the application to support reconfiguration by setting the Persist
bitstream generation option. However, the serial modes do not support device readback.
DS099 (v3.1) June 27, 2013
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Product Specification
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