XC3S5000-5FGG676C Datasheet, PDF (19/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
The DCI feature operates independently for each of the device’s eight banks. Each bank has an ‘N’ reference pin (VRN) and
a ‘P’ reference pin, (VRP), to calibrate driver and termination resistance. Only when using a DCI standard on a given bank
do these two pins function as VRN and VRP. When not using a DCI standard, the two pins function as user I/Os. As shown
in Figure 9, add an external reference resistor to pull the VRN pin up to V_CCO and another reference resistor to pull the VRP
pin down to GND. Also see Figure 42, page 116. Both resistors have the same value—commonly 50Ω—with one-percent
tolerance, which is either the characteristic impedance of the line or twice that, depending on the DCI standard in use.
Standards having a symbol name that contains the letters “DV2” use a reference resistor value that is twice the line
impedance. DCI adjusts the output driver impedance to match the reference resistors’ value or half that, according to the
standard. DCI always adjusts the on-chip termination resistors to directly match the reference resistors’ value.
X-Ref Target - Figure 9
One of eight
I/O Banks
VCCO
VRN
VRP
R_REF (1%)
R_REF (1%)
DS099-2_04_082104
Figure 9: Connection of Reference Resistors (R_REF)
The rules guiding the use of DCI standards on banks are as follows:
• No more than one DCI I/O standard with a Single Termination is allowed per bank.
• No more than one DCI I/O standard with a Split Termination is allowed per bank.
• Single Termination, Split Termination, Controlled- Impedance Driver, and Controlled-Impedance Driver with Half
Impedance can co-exist in the same bank.
See also The Organization of IOBs into Banks, immediately below, and DCI: User I/O or Digitally Controlled Impedance
Resistor Reference Input, page 115.
The Organization of IOBs into Banks
IOBs are allocated among eight banks, so that each side of the device has two banks, as shown in Figure 10. For all
packages, each bank has independent V_REF lines. For example, V_REF Bank 3 lines are separate from the V_REF lines going
to all other banks.
For the Very Thin Quad Flat Pack (VQ), Plastic Quad Flat Pack (PQ), Fine Pitch Thin Ball Grid Array (FT), and Fine Pitch Ball
Grid Array (FG) packages, each bank has dedicated V_CCO lines. For example, the V_CCO Bank 7 lines are separate from the
V_CCO lines going to all other banks. Thus, Spartan-3 devices in these packages support eight independent V_CCO supplies.
X-Ref Target - Figure 10
Bank 0
Bank 1
Bank 5
Bank 4
DS099-2_03_082104
Figure 10: Spartan-3 FPGA I/O Banks (Top View)
DS099 (v3.1) June 27, 2013
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Product Specification
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