XC3S5000-5FGG676C Datasheet, PDF (77/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 47: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
HSLVDCI_25
HSLVDCI_33
HSTL_I
HSTL_I_DCI
HSTL_III
HSTL_III_DCI
HSTL_I_18
HSTL_I_DCI_18
HSTL_II_18
HSTL_II_DCI_18
HSTL_III_18
HSTL_III_DCI_18
LVCMOS12
LVCMOS15
LVDCI_15
LVDCI_DV2_15
Slow
Fast
Slow
Fast
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
12 mA
Add the Adjustment Below
Speed Grade
-5
-4
0.27
0.31
0.28
0.32
0.60
0.69
0.59
0.68
0.19
0.22
0.20
0.23
0.18
0.21
0.17
0.19
–0.02
–0.01
0.75
0.86
0.28
0.32
0.28
0.32
7.60
8.73
7.42
8.53
6.67
7.67
3.16
3.63
2.70
3.10
2.41
2.77
4.55
5.23
3.76
4.32
3.57
4.11
3.55
4.09
3.00
3.45
3.11
3.57
1.71
1.96
1.44
1.66
1.26
1.44
1.11
1.27
1.51
1.74
1.32
1.52
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
77