XC3S5000-5FGG676C Datasheet, PDF (90/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 52: CLB Distributed RAM Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_SHCKO
Time from the active edge at the CLK input to data appearing on
the distributed RAM output
Setup Times
T_DS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the distributed RAM
T_AS
Setup time of the F/G address inputs before the active transition
at the CLK input of the distributed RAM
T_WS
Setup time of the write enable input before the active transition at
the CLK input of the distributed RAM
Hold Times
T_DH, T_AH, T_WH
Hold time of the BX, BY data inputs, the F/G address inputs, or
the write enable input after the active transition at the CLK input
of the distributed RAM
Clock Pulse Width
T_WPH, T_WPL Minimum High or Low pulse width at CLK input
-5
Min
Max
–
1.87
0.46
–
0.46
–
0.33
–
0
–
0.85
–
-4
Min Max
–
2.15
0.52
–
0.53
–
0.37
–
0
–
0.97
–
Units
ns
ns
ns
ns
ns
ns
Table 53: CLB Shift Register Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_REG
Time from the active edge at the CLK input to data appearing on
the shift register output
Setup Times
T_SRLDS
Setup time of data at the BX or BY input before the active
transition at the CLK input of the shift register
Hold Times
T_SRLDH
Hold time of the BX or BY data input after the active transition at
the CLK input of the shift register
Clock Pulse Width
T_WPH, T_WPL Minimum High or Low pulse width at CLK input
-5
Min
Max
–
3.30
0.46
–
0
–
0.85
–
-4
Min Max
–
3.79
0.52
–
0
–
0.97
–
Units
ns
ns
ns
ns
DS099 (v3.1) June 27, 2013
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Product Specification
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