XC3S5000-5FGG676C Datasheet, PDF (210/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
FG900: 900-lead Fine-pitch Ball Grid Array
The 900-lead fine-pitch ball grid array package, FG900, supports three different Spartan-3 devices, including the
XC3S2000, the XC3S4000, and the XC3S5000. The footprints for the XC3S4000 and XC3S5000 are identical, as shown in
Table 107 and Figure 55. The XC3S2000, however, has fewer I/O pins which consequently results in 68 unconnected pins
on the FG900 package, labeled as “N.C.” In Table 107 and Figure 55, these unconnected pins are indicated with a black
diamond symbol ().
All the package pins appear in Table 107 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S2000 pinout and the pinout for the XC3S4000 and XC3S5000, then that difference
is highlighted in Table 107. If the table entry is shaded, then there is an unconnected pin on the XC3S2000 that maps to a
user-I/O pin on the XC3S4000 and XC3S5000.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 107: FG900 Package Pinout
Bank
XC3S2000
Pin Name
XC3S4000, XC3S5000
Pin Name
0
IO
IO
0
IO
IO
0
IO
IO
0
IO
IO
0
IO
IO
0
IO/VREF_0
IO/VREF_0
0
IO/VREF_0
IO/VREF_0
0
IO_L01N_0/VRP_0
IO_L01N_0/VRP_0
0
IO_L01P_0/VRN_0
IO_L01P_0/VRN_0
0
IO_L02N_0
IO_L02N_0
0
IO_L02P_0
IO_L02P_0
0
IO_L03N_0
IO_L03N_0
0
IO_L03P_0
IO_L03P_0
0
IO_L04N_0
IO_L04N_0
0
IO_L04P_0
IO_L04P_0
0
IO_L05N_0
IO_L05N_0
0
IO_L05P_0/VREF_0
IO_L05P_0/VREF_0
0
IO_L06N_0
IO_L06N_0
0
IO_L06P_0
IO_L06P_0
0
IO_L07N_0
IO_L07N_0
0
IO_L07P_0
IO_L07P_0
0
IO_L08N_0
IO_L08N_0
0
IO_L08P_0
IO_L08P_0
0
IO_L09N_0
IO_L09N_0
0
IO_L09P_0
IO_L09P_0
FG900 Pin
Number
E15
K15
D13
K13
G8
F9
C4
B4
A4
B5
A5
D5
E6
C6
B6
F6
F7
D7
C7
F8
E8
D8
C8
B8
A8
Type
I/O
I/O
I/O
I/O
I/O
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
210