XC3S5000-5FGG676C Datasheet, PDF (17/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Table 10: DCI I/O Standards
Category of Signal
Standard
Signal Standard
(IOSTANDARD)
Single-Ended
Gunning
Transceiver Logic
High-Speed
Transceiver Logic
Low-Voltage CMOS
Hybrid HSTL Input
and LVCMOS Output
Stub Series
Terminated Logic⁽³⁾
Differential
Low-Voltage
Differential Signaling
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_III_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
DIFF_HSTL_II_18_DCI
HSTL_III_DCI_18
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33⁽²⁾
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
SSTL18_I_DCI
SSTL2_I_DCI
SSTL2_II_DCI
DIFF_SSTL2_II_DCI
LVDS_25_DCI
LVDSEXT_25_DCI
V_CCO (V)
For Outputs For Inputs
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
1.5
1.5
1.8
1.8
2.5
2.5
3.3
3.3
1.5
1.5
1.8
1.8
2.5
2.5
3.3
3.3
1.5
1.5
1.8
1.8
2.5
2.5
3.3
3.3
1.8
1.8
2.5
2.5
2.5
2.5
N/A
2.5
N/A
2.5
V_REF for
Inputs (V)
Termination Type
At Output
At Input
0.8
Single
Single
1.0
0.75
None
Split
0.9
None
Single
0.9
None
Split
0.9
Split
1.1
None
Single
–
–
Controlled
–
impedance driver
–
None
–
–
Controlled driver
with
–
half-impedance
–
0.75
0.9
1.25
Controlled
impedance driver
None
1.65
0.9
25Ω driver
1.25
25Ω driver
Split
1.25
Split with 25Ω driver
–
–
None
Split on each
line of pair
Notes:
1. DCI signal standards are not supported in Bank 5 of any Spartan-3 FPGA packaged in a VQ100, CP132, or TQ144 package.
2. Equivalent to LVTTL DCI.
3. The SSTL18_II signal standard does not have a DCI equivalent.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
17