XC3S5000-5FGG676C Datasheet, PDF (175/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
FG456: 456-lead Fine-pitch Ball Grid Array
The 456-lead fine-pitch ball grid array package, FG456, supports four different Spartan-3 devices, including the XC3S400,
the XC3S1000, the XC3S1500, and the XC3S2000. The footprints for the XC3S1000, the XC3S1500, and the XC3S2000
are identical, as shown in Table 100 and Figure 51. The XC3S400, however, has fewer I/O pins which consequently results
in 69 unconnected pins on the FG456 package, labeled as “N.C.” In Table 100 and Figure 51, these unconnected pins are
indicated with a black diamond symbol ().
All the package pins appear in Table 100 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S400 pinout and the pinout for the XC3S1000, the XC3S1500, or the XC3S2000,
then that difference is highlighted in Table 100. If the table entry is shaded grey, then there is an unconnected pin on the
XC3S400 that maps to a user-I/O pin on the XC3S1000, XC3S1500, and XC3S2000. If the table entry is shaded tan, then
the unconnected pin on the XC3S400 maps to a VREF-type pin on the XC3S1000, the XC3S1500, or the XC3S2000. If the
other VREF pins in the bank all connect to a voltage reference to support a special I/O standard, then also connect the N.C.
pin on the XC3S400 to the same VREF voltage. This provides maximum flexibility as you could potentially migrate a design
from the XC3S400 device to an XC3S1000, an XC3S1500, or an XC3S2000 FPGA without changing the printed circuit
board.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 100: FG456 Package Pinout
Bank
3S400
Pin Name
3S1000, 3S1500, 3S2000 FG456
Pin Name
Pin Number
0
IO
IO
A10
0
IO
IO
D9
0
IO
IO
D10
0
IO
IO
F6
0
IO/VREF_0
IO/VREF_0
A3
0
IO/VREF_0
IO/VREF_0
C7
0
N.C. ()
IO/VREF_0
E5
0
IO/VREF_0
IO/VREF_0
F7
0
IO_L01N_0/VRP_0
IO_L01N_0/VRP_0
B4
0
IO_L01P_0/VRN_0
IO_L01P_0/VRN_0
A4
0
IO_L06N_0
IO_L06N_0
D5
0
IO_L06P_0
IO_L06P_0
C5
0
IO_L09N_0
IO_L09N_0
B5
0
IO_L09P_0
IO_L09P_0
A5
0
IO_L10N_0
IO_L10N_0
E6
0
IO_L10P_0
IO_L10P_0
D6
0
IO_L15N_0
IO_L15N_0
C6
0
IO_L15P_0
IO_L15P_0
B6
0
IO_L16N_0
IO_L16N_0
E7
0
IO_L16P_0
IO_L16P_0
D7
0
N.C. ()
IO_L19N_0
B7
0
N.C. ()
IO_L19P_0
A7
Type
I/O
I/O
I/O
I/O
VREF
VREF
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
175