XC3S5000-5FGG676C Datasheet, PDF (131/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 86: Spartan-3 FPGA Package Thermal Characteristics (Cont’d)
Package
Device
Junction-to-
Case (θ_JC)
Junction-to-B ^{Junction-to-Ambient (θJA) at Different Air Flows}
oard (θ_JB)
Still Air
(0 LFM)
250 LFM 500 LFM 750 LFM
Units
XC3S4000
1.9
FG(G)1156⁽¹⁾
XC3S5000
1.9
–
14.7
11.4
10.1
9.0
°C/Watt
8.9
14.5
11.3
10.0
8.9
°C/Watt
Notes:
1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
VQ100: 100-lead Very-Thin Quad Flat Package
The XC3S50 and the XC3S200 devices are available in the 100-lead very-thin quad flat package, VQ100. Both devices
share a common footprint for this package as shown in Table 87 and Figure 44.
All the package pins appear in Table 87 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 87: VQ100 Package Pinout
Bank
XC3S50
XC3S200
Pin Name
0
IO_L01N_0/VRP_0
0
IO_L01P_0/VRN_0
0
IO_L31N_0
0
IO_L31P_0/VREF_0
0
IO_L32N_0/GCLK7
0
IO_L32P_0/GCLK6
0
VCCO_0
1
IO
1
IO_L01N_1/VRP_1
1
IO_L01P_1/VRN_1
1
IO_L31N_1/VREF_1
1
IO_L31P_1
1
IO_L32N_1/GCLK5
1
IO_L32P_1/GCLK4
1
VCCO_1
2
IO_L01N_2/VRP_2
2
IO_L01P_2/VRN_2
2
IO_L21N_2
2
IO_L21P_2
2
IO_L24N_2
2
IO_L24P_2
VQ100
Pin
Number
P97
P96
P92
P91
P90
P89
P94
P81
P80
P79
P86
P85
P88
P87
P83
P75
P74
P72
P71
P68
P67
Type
DCI
DCI
I/O
VREF
GCLK
GCLK
VCCO
I/O
DCI
DCI
VREF
I/O
GCLK
GCLK
VCCO
DCI
DCI
I/O
I/O
I/O
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
131