XC3S5000-5FGG676C Datasheet, PDF (136/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
CP132: 132-Ball Chip-Scale Package
Note: The CP132 and CPG132 packages are discontinued. See
www.xilinx.com/support/documentation/spartan-3.htm#19600.
The pinout and footprint for the XC3S50 in the 132-ball chip-scale package, CP132, appear in Table 89 and Figure 45.
All the package pins appear in Table 89 and are sorted by bank number, then by pin name. Pins that form a differential I/O
pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier.
The CP132 footprint has eight I/O banks. However, the voltage supplies for the two I/O banks along an edge are connected
together internally. Consequently, there are four output voltage supplies, labeled VCCO_TOP, VCCO_RIGHT,
VCCO_BOTTOM, and VCCO_LEFT.
Pinout Table
Table 89: CP132 Package Pinout
Bank
XC3S50 Pin Name
0
IO_L01N_0/VRP_0
0
IO_L01P_0/VRN_0
0
IO_L27N_0
0
IO_L27P_0
0
IO_L30N_0
0
IO_L30P_0
0
IO_L31N_0
0
IO_L31P_0/VREF_0
0
IO_L32N_0/GCLK7
0
IO_L32P_0/GCLK6
1
IO_L01N_1/VRP_1
1
IO_L01P_1/VRN_1
1
IO_L27N_1
1
IO_L27P_1
1
IO_L28N_1
1
IO_L28P_1
1
IO_L31N_1/VREF_1
1
IO_L31P_1
1
IO_L32N_1/GCLK5
1
IO_L32P_1/GCLK4
2
IO_L01N_2/VRP_2
2
IO_L01P_2/VRN_2
2
IO_L20N_2
2
IO_L20P_2
2
IO_L21N_2
2
IO_L21P_2
2
IO_L23N_2/VREF_2
2
IO_L23P_2
2
IO_L24N_2
CP132
Ball
A3
C4
C5
B5
B6
A6
C7
B7
A7
C8
A13
B13
C11
A12
A11
B11
C9
A10
A8
A9
D12
C14
E12
E13
E14
F12
F13
F14
G12
Type
DCI
DCI
I/O
I/O
I/O
I/O
I/O
VREF
GCLK
GCLK
DCI
DCI
I/O
I/O
I/O
I/O
VREF
I/O
GCLK
GCLK
DCI
DCI
I/O
I/O
I/O
I/O
VREF
I/O
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
136