XC3S5000-5FGG676C Datasheet, PDF (65/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 36: DC Characteristics of User I/Os Using Single-Ended Standards (Cont’d)
Signal Standard
(IOSTANDARD) and Current
Drive Attribute (mA)
LVCMOS33⁽⁴⁾
2
4
6
8
12
16
24
LVDCI_33,
LVDCI_DV2_33
LVTTL⁽⁴⁾
2
4
6
8
12
16
24
PCI33_3
SSTL18_I
SSTL18_I_DCI
SSTL18_II
SSTL2_I
SSTL2_I_DCI
SSTL2_II⁽⁷⁾
SSTL2_II_DCI⁽⁷⁾
Test Conditions
I_OL
(mA)
I_OH
(mA)
2
–2
4
–4
6
–6
8
–8
12
–12
16
–16
24
–24
Note 3
Note 3
2
4
6
8
12
16
24
Note 6
6.7
Note 3
13.4
8.1
Note 3
16.2
Note 3
–2
–4
–6
–8
–12
–16
–24
Note 6
–6.7
Note 3
–13.4
–8.1
Note 3
–16.2
Note 3
Logic Level Characteristics
V_OL
Max (V)
V_OH
Min (V)
0.4
V_CCO – 0.4
0.4
2.4
0.10V_CCO
V_TT – 0.475
V_TT – 0.475
V_TT – 0.61
V_TT – 0.81
0.90V_CCO
V_TT + 0.475
V_TT + 0.475
V_TT + 0.61
V_TT + 0.81
Notes:
1. The numbers in this table are based on the conditions set forth in Table 32 and Table 35.
2. Descriptions of the symbols used in this table are as follows:
I_OL – the output current condition under which VOL is tested
I_OH – the output current condition under which VOH is tested
V_OL – the output voltage that indicates a Low logic level
V_OH – the output voltage that indicates a High logic level
V_IL – the input voltage that indicates a Low logic level
V_IH – the input voltage that indicates a High logic level
V_CCO – the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs
V_REF – the reference voltage for setting the input switching threshold
V_TT – the voltage applied to a resistor termination
3. Tested according to the standard’s relevant specifications. When using the DCI version of a standard on a given I/O bank, that bank will consume
more power than if the non-DCI version had been used instead. The additional power is drawn for the purpose of impedance-matching at the I/O pins.
A portion of this power is dissipated in the two RREF resistors.
4. For the LVCMOS and LVTTL standards: the same V_OL and V_OH limits apply for both the Fast and Slow slew attributes.
5. All dedicated output pins (CCLK, DONE, and TDO) and dual-purpose totem-pole output pins (D0-D7 and BUSY/DOUT) exhibit the characteristics of
LVCMOS25 with 12 mA drive and slow slew rate. For information concerning the use of 3.3V signals, see 3.3V-Tolerant Configuration Interface,
page 47.
6. Tested according to the relevant PCI specifications. For more information, see XAPP457.
7. The minimum usable V_TT voltage is 1.25V.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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