XC3S5000-5FGG676C Datasheet, PDF (20/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
In contrast, the 144-pin Thin Quad Flat Pack (TQ144) package and the 132-pin Chip-Scale Package (CP132) tie V_CCO
together internally for the pair of banks on each side of the device. For example, the V_CCO Bank 0 and the V_CCO Bank 1 lines
are tied together. The interconnected bank-pairs are 0/1, 2/3, 4/5, and 6/7. As a result, Spartan-3 devices in the CP132 and
TQ144 packages support four independent V_CCO supplies.
Note: The CP132 package is discontinued. See http://www.xilinx.com/support/documentation /spartan-3_customer_notices.htm.
Spartan-3 FPGA Compatibility
Within the Spartan-3 family, all devices are pin-compatible by package. When the need for future logic resources outgrows
the capacity of the Spartan-3 device in current use, a larger device in the same package can serve as a direct replacement.
Larger devices may add extra V_REF and V_CCO lines to support a greater number of I/Os. In the larger device, more pins can
convert from user I/Os to V_REF lines. Also, additional V_CCO lines are bonded out to pins that were “not connected” in the
smaller device. Thus, it is important to plan for future upgrades at the time of the board’s initial design by laying out
connections to the extra pins.
The Spartan-3 family is not pin-compatible with any previous Xilinx FPGA family or with other platforms among the
Spartan-3 Generation FPGAs.
Rules Concerning Banks
When assigning I/Os to banks, it is important to follow the following V_CCO rules:
• Leave no V_CCO pins unconnected on the FPGA.
• Set all V_CCO lines associated with the (interconnected) bank to the same voltage level.
• The V_CCO levels used by all standards assigned to the I/Os of the (interconnected) bank(s) must agree. The Xilinx
development software checks for this. Tables 8, 9, and 10 describe how different standards use the V_CCO supply.
• Only one of the following standards is allowed on outputs per bank: LVDS, LDT, LVDS_EXT, or RSDS. This restriction is
for the eight banks in each device, even if the V_CCO levels are shared across banks, as in the CP132 and TQ144
packages.
• If none of the standards assigned to the I/Os of the (interconnected) bank(s) uses V_CCO, tie all associated V_CCO lines to
2.5V.
• In general, apply 2.5V to V_CCO Bank 4 from power-on to the end of configuration. Apply the same voltage to V_CCO Bank
5 during parallel configuration or a Readback operation. For information on how to program the FPGA using 3.3V
signals and power, see the 3.3V-Tolerant Configuration Interface section.
If any of the standards assigned to the Inputs of the bank use V_REF, then observe the following additional rules:
• Connect all V_REF pins within the bank to the same voltage level.
• The V_REF levels used by all standards assigned to the Inputs of the bank must agree. The Xilinx development software
checks for this. Tables 8 and 10 describe how different standards use the V_REF supply.
If none of the standards assigned to the Inputs of a bank use V_REF for biasing input switching thresholds, all associated V_REF
pins function as User I/Os.
Exceptions to Banks Supporting I/O Standards
Bank 5 of any Spartan-3 device in a VQ100, CP132, or TQ144 package does not support DCI signal standards. In this case,
bank 5 has neither VRN nor VRP pins.
Furthermore, banks 4 and 5 of any Spartan-3 device in a VQ100 package do not support signal standards using V_REF (see
Table 8). In this case, the two banks do not have any V_REF pins.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
20