XC3S5000-5FGG676C Datasheet, PDF (56/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Revision History
Date
04/11/2003
05/19/2003
07/11/2003
08/24/2004
08/19/2005
04/03/2006
04/26/2006
05/25/2007
11/30/2007
06/25/2008
12/04/2009
10/29/2012
06/27/2013
Version No.
1.0
1.1
1.2
1.3
1.4
2.0
2.1
2.2
2.3
2.4
2.5
3.0
3.1
Description
Initial Xilinx release
Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions.
Explained the configuration port Persist option in Slave Parallel Mode (SelectMAP) section. Updated
Figure 8 and Double-Data-Rate Transmission section to indicate that DDR clocking for the XC3S50 is the
same as that for all other Spartan-3 devices. Updated description of I/O voltage tolerance in ESD
Protection section. In Table 10, changed input termination type for DCI version of the LVCMOS standard
to None. Added additional flexibility for making DLL connections in Figure 21 and accompanying text. In
the Configuration section, inserted an explanation of how to choose power supplies for the configuration
interface, including guidelines for achieving 3.3V-tolerance.
Showed inversion of 3-state signal (Figure 7). Clarified description of pull-up and pull-down resistors
(Table 6 and page 13). Added information on operating block RAM with multipliers to page 26. Corrected
output buffer name in Figure 21. Corrected description of how DOUT is synchronized to CCLK (page 47).
Corrected description of WRITE_FIRST and READ_FIRST in Table 13. Added note regarding address
setup and hold time requirements whenever a block RAM port is enabled (Table 13). Added information
in the maximum length of a Configuration daisy-chain. Added reference to XAPP453 in 3.3V-Tolerant
Configuration Interface section. Added information on the STATUS[2] DCM output (Table 23). Added
information on CCLK behavior and termination recommendations to Configuration. Added Additional
Configuration Details section. Added Powering Spartan-3 FPGAs section. Removed GSR from Figure 31
because its timing is not programmable.
Updated Figure 7. Updated Figure 14. Updated Table 10. Updated Figure 22. Corrected Platform Flash
supply voltage name and value in Figure 26 and Figure 28. Added No Internal Charge Pumps or
Free-Running Oscillators. Corrected a few minor typographical errors.
Added more information on the pull-up resistors that are active during configuration to Configuration.
Added information to Boundary-Scan (JTAG) Mode about potential interactions when configuring via
JTAG if the mode select pins are set for other than JTAG.
Added Spartan-3 FPGA Design Documentation. Noted SSTL2_I_DCI 25-Ohm driver in Table 10 and
Table 11. Added note that pull-down is active during boundary scan tests.
Updated links to documentation on xilinx.com.
Added HSLVDCI to Table 10. Updated formatting and links.
Updated HSLVDCI description in Digitally Controlled Impedance (DCI). Updated the low-voltage
differential signaling V_CCO values in Table 10. Noted that the CP132 package is being discontinued in The
Organization of IOBs into Banks. Updated rule 4 in Rules Concerning Banks. Added software version
requirement in The Fixed Phase Mode.
Added Notice of Disclaimer. Per XCN07022, updated the discontinued FG1156 and FGG1156 package
discussion throughout document. Per XCN08011, updated the discontinued CP132 and CPG132
package discussion throughout document. This product is not recommended for new designs.
Removed banner. This product IS recommended for new designs.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
56