XC3S5000-5FGG676C Datasheet, PDF (54/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Additional Configuration Details
Additional details about the Spartan-3 FPGA configuration architecture and command set are available in UG332: Spartan-3
Generation Configuration User Guide and in application note XAPP452: Spartan-3 Advanced Configuration Architecture.
Powering Spartan-3 FPGAs
Voltage Regulators
Various power supply manufacturers offer complete power solutions for Xilinx FPGAs, including some with integrated
multi-rail regulators specifically designed for Spartan-3 FPGAs. The Xilinx Power Corner web page provides links to vendor
solution guides as well as Xilinx power estimation and analysis tools.
Power Distribution System (PDS) Design and Bypass/Decoupling Capacitors
Good power distribution system (PDS) design is important for all FPGA designs, especially for high-performance
applications. Proper design results in better overall performance, lower clock and DCM jitter, and a generally more robust
system. Before designing the printed circuit board (PCB) for the FPGA design, review application note XAPP623: Power
Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors.
Power-On Behavior
Spartan-3 FPGAs have a built-in Power-On Reset (POR) circuit that monitors the three power rails required to successfully
configure the FPGA. At power-up, the POR circuit holds the FPGA in a reset state until the V_CCINT, V_CCAUX, and V_CCO Bank
4 supplies reach their respective input threshold levels (see Table 29, page 59). After all three supplies reach their respective
threshold, the POR reset is released and the FPGA begins its configuration process.
Because the three supply inputs must be valid to release the POR reset and can be supplied in any order, there are no
specific voltage sequencing requirements. However, applying the FPGA’s V_CCAUX supply before the V_CCINT supply uses the
least I_CCINT current.
Once all three supplies are valid, the minimum current required to power-on the FPGA is equal to the worst-case quiescent
current, as specified in Table 34, page 62. Spartan-3 FPGAs do not require Power-On Surge (POS) current to successfully
configure.
Surplus I_CCINT if V_CCINT Applied before V_CCAUX
If the V_CCINT supply is applied before the V_CCAUX supply, the FPGA may draw a surplus I_CCINT current in addition to the
I_CCINT quiescent current levels specified in Table 34. The momentary additional I_CCINT surplus current might be a few
hundred milliamperes under nominal conditions, significantly less than the instantaneous current consumed by the bypass
capacitors at power-on. However, the surplus current immediately disappears when the V_CCAUX supply is applied, and, in
response, the FPGA’s I_CCINT quiescent current demand drops to the levels specified in Table 34. The FPGA does not use
nor does it require the surplus current to successfully power-on and configure. If applying V_CCINT- before V_CCAUX, ensure
that the regulator does not have a foldback feature that could inadvertently shut down in the presence of the surplus current.
Maximum Allowed V_CCINT Ramp Rate on Early Devices, if V_VCCINTSupply is Last in Sequence
All devices with a mask revision code ‘E’ or later do not have a V_CCINT ramp rate requirement. See Mask and Fab Revisions,
page 58.
Early Spartan-3 FPGAs were produced at a 200 mm wafer production facility and are identified by a fabrication/process
code of "FQ" on the device top marking, as shown in Package Marking, page 5. These "FQ" devices have a maximum
V_CCINT ramp rate requirement if and only if V_CCINT is the last supply to ramp, after the V_CCAUX and V_CCO Bank 4 supplies.
This maximum ramp rate appears as T_CCINT in Table 30, page 60.
Minimum Allowed V_CCO Ramp Rate on Early Devices
Devices shipped since 2006 essentially have no V_CCO ramp rate limits, shown in Table 30, page 60. Similarly, all devices
with a mask revision code ‘E’ or later do not have a V_CCO ramp rate limit. See Mask and Fab Revisions, page 58.
DS099 (v3.1) June 27, 2013
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Product Specification
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