XC3S5000-5FGG676C Datasheet, PDF (95/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 59: Switching Characteristics for the DLL (Cont’d)
Symbol
Lock Time
LOCK_DLL
Delay Lines
DCM_TAP
Description
Frequency Mode /
FCLKIN Range
Device
Speed Grade
-5
-4
Units
Min Max Min Max
When using the DLL alone: 18 MHz ≤ F_CLKIN ≤ 30 MHz
All
The time from deassertion at
the DCM’s Reset input to the ^{30 MHz < FCLKIN ≤ 40 MHz}
rising transition at its
LOCKED output. When the
40 MHz < F_CLKIN ≤ 50 MHz
DCM is locked, the CLKIN and ^{50 MHz < F}CLKIN ^{≤ 60 MHz}
CLKFB signals are in phase
F_CLKIN > 60 MHz
– 2.88 – 2.88 ms
– 2.16 – 2.16 ms
– 1.20 – 1.20 ms
– 0.60 – 0.60 ms
– 0.48 – 0.48 ms
Delay tap resolution
All
All
30.0 60.0 30.0 60.0 ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32 and Table 58.
2. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
3. Only mask revision ‘E’ and later devices (see Mask and Fab Revisions, page 58) and all revisions of the XC3S50 and the XC3S1000 support
DLL feedback using the CLK2X output. For all other Spartan-3 devices, use feedback from the CLK0 output (instead of the CLK2X output)
and set the CLK_FEEDBACK attribute to 1X.
4. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
5. This specification only applies if the attribute DUTY_CYCLE_CORRECTION = TRUE.
Digital Frequency Synthesizer (DFS)
Table 60: Recommended Operating Conditions for the DFS
Symbol
Description
Frequency
Mode
Input Frequency Ranges⁽²⁾
F_CLKIN
CLKIN_FREQ_FX
Input Clock Jitter Tolerance⁽³⁾
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
Frequency for the CLKIN input
All
Cycle-to-cycle jitter at the CLKIN
input
Period jitter at the CLKIN input
Low
High
All
Speed Grade
-5
-4
Min Max Min Max
Units
1
280
1
280 MHz
–
±300
–
±300 ps
–
±150
–
±150 ps
–
±1
–
±1
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 58.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
DS099 (v3.1) June 27, 2013
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Product Specification
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