XC3S5000-5FGG676C Datasheet, PDF (120/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
X-Ref Target - Figure 43
TDI
TMS
JTAG Port
Data In
Data Out
Mode Select
TDO
TCK
Clock
Figure 43: JTAG Port
DS099_4_04_020811
IDCODE Register
Spartan-3 FPGAs contain a 32-bit identification register called the IDCODE register, as defined in the IEEE 1149.1 JTAG
standard. The fixed value electrically identifies the manufacture (Xilinx) and the type of device being addressed over a JTAG
chain. This register allows the JTAG host to identify the device being tested or programmed via JTAG. See Table 78.
Using JTAG Port After Configuration
The JTAG port is always active and available before, during, and after FPGA configuration. Add the BSCAN_SPARTAN3
primitive to the design to create user-defined JTAG instructions and JTAG chains to communicate with internal logic.
Furthermore, the contents of the User ID register within the JTAG port can be specified as a Bitstream Generation option.
By default, the 32-bit User ID register contains 0xFFFFFFFF.
Table 78: Spartan-3 JTAG IDCODE Register Values (hexadecimal)
Part Number
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
IDCODE Register
0x0140C093
0x01414093
0x0141C093
0x01428093
0x01434093
0x01440093
0x01448093
0x01450093
Precautions When Using the JTAG Port in 3.3V Environments
The JTAG port is powered by the +2.5V VCCAUX power supply. When connecting to a 3.3V interface, the JTAG input pins
must be current-limited using a series resistor. Similarly, the TDO pin is a CMOS output powered from +2.5V. The TDO
output can directly drive a 3.3V input but with reduced noise immunity. See 3.3V-Tolerant Configuration Interface, page 47.
See also XAPP453: The 3.3V Configuration of Spartan-3 FPGAs for additional details.
The following interface precautions are recommended when connecting the JTAG port to a 3.3V interface.
• Avoid actively driving the JTAG input signals High with 3.3V signal levels. If required in the application, use series
current-limiting resistors to keep the current below 10 mA per pin.
• If possible, drive the FPGA JTAG inputs with drivers that can be placed in high-impedance (Hi-Z) after using the JTAG
port. Alternatively, drive the FPGA JTAG inputs with open-drain outputs, which only drive Low. In both cases, pull-up
resistors are required. The FPGA JTAG pins have pull-up resistors to VCCAUX before configuration and optional
pull-up resistors after configuration, controlled by Bitstream Options, page 125.
DS099 (v3.1) June 27, 2013
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Product Specification
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