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XC3S5000-5FGG676C Datasheet, PDF (60/272 Pages) Xilinx, Inc – Introduction and Ordering Information
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 30: Power Voltage Ramp Time Requirements
Symbol
Description
TCCO
TCCINT
VCCO ramp time for all eight banks
VCCINT ramp time, only if VCCINT is last in
three-rail power-on sequence
Device
All
All
Package
All
All
Min
No limit(4)
No limit
Max
–
No limit(5)
Units
N/A
N/A
Notes:
1. If a limit exists, this specification is based on characterization.
2. The ramp time is measured from 10% to 90% of the full nominal voltage swing for all I/O standards.
3. For information on power-on current needs, see Power-On Behavior, page 54
4. For mask revisions earlier than revision E (see Mask and Fab Revisions, page 58), TCCO min is limited to 2.0 ms for the XC3S200 and
XC3S400 devices in QFP packages, and limited to 0.6 ms for the XC3S200, XC3S400, XC3S1500, and XC3S4000 devices in the FT and
FG packages.
5. For earlier device versions with the FQ fabrication/process code (see Mask and Fab Revisions, page 58), TCCINT max is limited to 500 µs.
Table 31: Power Voltage Levels Necessary for Preserving RAM Contents
Symbol
Description
Min
Units
VDRINT
VDRAUX
VCCINT level required to retain RAM data
VCCAUX level required to retain RAM data
1.0
V
2.0
V
Notes:
1. RAM contents include data stored in CMOS configuration latches.
2. The level of the VCCO supply has no effect on data retention.
3. If a brown-out condition occurs where VCCAUX or VCCINT drops below the retention voltage, then VCCAUX or VCCINT must drop below the
minimum power-on reset voltage indicated in Table 29 in order to clear out the device configuration content.
Table 32: General Recommended Operating Conditions
Symbol
Description
Min
Nom
Max
Units
TJ
Junction temperature
Commercial
Industrial
0
25
–40
25
85
°C
100
°C
VCCINT
VCCO (1)
VCCAUX
ΔVCCAUX(2)
VIN(3)
Internal supply voltage
Output driver supply voltage
Auxiliary supply voltage
Voltage variance on VCCAUX when using a DCM
Voltage applied to all User I/O pins and
Dual-Purpose pins relative to GND(4)(6)
VCCO = 3.3V, IO
VCCO = 3.3V, IO_Lxxy(7)
VCCO ≤ 2.5V, IO
VCCO ≤ 2.5V, IO_Lxxy(7)
Voltage applied to all Dedicated pins relative to GND(5)
1.140
1.140
2.375
–
–0.3
–0.3
–0.3
–0.3
–0.3
1.200
–
2.500
–
–
–
–
–
–
1.260
V
3.465
V
2.625
V
10
mV/ms
3.75
V
3.75
V
VCCO + 0.3(4)
V
VCCO + 0.3(4)
V
VCCAUX+ 0.3(5)
V
Notes:
1. The VCCO range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended VCCO range
specific to each of the single-ended I/O standards is given in Table 35, and that specific to the differential standards is given in Table 37.
2. Only during DCM operation is it recommended that the rate of change of VCCAUX not exceed 10 mV/ms.
3. Input voltages outside the recommended range are permissible provided that the IIK input diode clamp diode rating is met. Refer to Table 28.
4. Each of the User I/O and Dual-Purpose pins is associated with one of the VCCO rails. Meeting the VIN limit ensures that the internal diode
junctions that exist between these pins and their associated VCCO and GND rails do not turn on. The absolute maximum rating is provided
in Table 28.
5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures
that the internal diode junctions that exist between each of these pins and the VCCAUX and GND rails do not turn on.
6. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3
Generation FPGAs.
7. For single-ended signals that are placed on a differential-capable I/O, VIN of –0.2V to –0.3V is supported but can cause increased leakage
between the two pins. See the Parasitic Leakage section in UG331, Spartan-3 Generation FPGA User Guide.
DS099 (v3.1) June 27, 2013
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