XC3S5000-5FGG676C Datasheet, PDF (59/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 28: Absolute Maximum Ratings (Cont’d)
Symbol
Description
Conditions
Min
Max
Units
I_IK
V_ESD
Input clamp current per I/O pin
Electrostatic Discharge Voltage pins relative
to GND
–0.5 V < V_IN < (V_CCO + 0.5 V)
Human body model
Charged device model
–
±100
mA
–
±2000
V
–
±500
V
Machine model
–
±200
V
T_J
T_SOL
T_STG
Junction temperature
Soldering temperature⁽⁴⁾
Storage temperature
–
125
°C
–
220
°C
–65
150
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not
implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
2. All User I/O and Dual-Purpose pins (DIN/D0, D1–D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) draw power from the V_CCO power rail of
the associated bank. Keeping VIN within 500 mV of the associated V_CCO rails or ground rail ensures that the internal diode junctions that
exist between each of these pins and the V_CCO and GND rails do not turn on. Table 32 specifies the V_CCO range used to determine the max
limit. Input voltages outside the –0.5V to V_CCO+0.5V voltage range are permissible provided that the I_IK input clamp diode rating is met and
no more than 100 pins exceed the range simultaneously. Prolonged exposure to such current may compromise device reliability. A sustained
current of 10 mA will not compromise device reliability. See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing
Single-Ended Signals to User I/O Pins on Spartan-3 Generation FPGAs for more details. The VIN limits apply to both the DC and AC
components of signals. Simple application solutions are available that show how to handle overshoot/undershoot as well as achieve PCI
compliance. Refer to the following application notes: XAPP457, Powering and Configuring Spartan-3 Generation FPGAs in Compliant PCI
Applications and XAPP659, Virtex®-II Pro / Virtex-II Pro X 3.3V I/O Design Guidelines.
3. All Dedicated pins (M0–M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) draw power from the V_CCAUX rail (2.5V).
Meeting the V_IN max limit ensures that the internal diode junctions that exist between each of these pins and the V_CCAUX rail do not turn on.
Table 32 specifies the V_CCAUX range used to determine the max limit. When V_CCAUX is at its maximum recommended operating level
(2.625V), V_IN max < 3.125V. As long as the V_IN max specification is met, oxide stress is not possible. For information concerning the use of
3.3V signals, see the 3.3V-Tolerant Configuration Interface, page 47. See also XAPP459.
4. For soldering guidelines, see UG112, Device Packaging and Thermal Characteristics and XAPP427, Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
Table 29: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
V_CCINTT
V_CCAUXT
V_CCO4T
Threshold for the V_CCINT supply
Threshold for the V_CCAUX supply
Threshold for the V_CCO Bank 4 supply
0.4
1.0
V
0.8
2.0
V
0.4
1.0
V
Notes:
1. V_CCINT, V_CCAUX, and V_CCO supplies may be applied in any order. When applying V_CCINT power before V_CCAUX power, the FPGA may draw
a surplus current in addition to the quiescent current levels specified in Table 34. Applying V_CCAUX eliminates the surplus current. The FPGA
does not use any of the surplus current for the power-on process. For this power sequence, make sure that regulators with foldback features
will not shut down inadvertently.
2. To ensure successful power-on, V_CCINT, V_CCO Bank 4, and V_CCAUX supplies must rise through their respective threshold-voltage ranges
with no dips at any point.
3. If a brown-out condition occurs where V_CCAUX or V_CCINT drops below the retention voltage indicated in Table 31, then V_CCAUX or V_CCINT
must drop below the minimum power-on reset voltage in order to clear out the device configuration content.
DS099 (v3.1) June 27, 2013
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Product Specification
59