XC3S5000-5FGG676C Datasheet, PDF (190/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
FG676: 676-lead Fine-pitch Ball Grid Array
The 676-lead fine-pitch ball grid array package, FG676, supports five different Spartan-3 devices, including the XC3S1000,
XC3S1500, XC3S2000, XC3S4000, and XC3S5000. All five have nearly identical footprints but are slightly different,
primarily due to unconnected pins on the XC3S1000 and XC3S1500. For example, because the XC3S1000 has fewer I/O
pins, this device has 98 unconnected pins on the FG676 package, labeled as “N.C.” In Table 103 and Figure 53, these
unconnected pins are indicated with a black diamond symbol (). The XC3S1500, however, has only two unconnected pins,
also labeled “N.C.” in the pinout table but indicated with a black square symbol ().
All the package pins appear in Table 103 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S1000, XC3S1500, XC3S2000, XC3S4000, and XC3S5000 pinouts, then that
difference is highlighted in Table 103. If the table entry is shaded grey, then there is an unconnected pin on either the
XC3S1000 or XC3S1500 that maps to a user-I/O pin on the XC3S2000, XC3S4000, and XC3S5000. If the table entry is
shaded tan, then the unconnected pin on either the XC3S1000 or XC3S1500 maps to a VREF-type pin on the XC3S2000,
XC3S4000, and XC3S5000. If the other VREF pins in the bank all connect to a voltage reference to support a special I/O
standard, then also connect the N.C. pin on the XC3S1000 or XC3S1500 to the same VREF voltage. This provides
maximum flexibility as you could potentially migrate a design from the XC3S1000 through to the XC3S5000 FPGA without
changing the printed circuit board.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip.
Pinout Table
Table 103: FG676 Package Pinout
Bank
XC3S1000
Pin Name
XC3S1500
Pin Name
0 IO
IO
0 IO
IO
0 IO
IO
0 IO
IO
0 N.C. ()
IO
0 IO
IO
0 IO
IO
0 IO
IO
0 IO
IO
0 IO/VREF_0
IO/VREF_0
0 IO/VREF_0
IO/VREF_0
0 IO/VREF_0
IO/VREF_0
0 IO_L01N_0/VRP_0 IO_L01N_0/VRP_0
0 IO_L01P_0/VRN_0 IO_L01P_0/VRN_0
0 IO_L05N_0
IO_L05N_0
0 IO_L05P_0/VREF_0 IO_L05P_0/VREF_0
0 IO_L06N_0
IO_L06N_0
0 IO_L06P_0
IO_L06P_0
0 IO_L07N_0
IO_L07N_0
0 IO_L07P_0
IO_L07P_0
0 IO_L08N_0
IO_L08N_0
0 IO_L08P_0
IO_L08P_0
XC3S2000
Pin Name
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L05N_0
IO_L05P_0/VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
XC3S4000
Pin Name
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L05N_0
IO_L05P_0/VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
XC3S5000
Pin Name
IO_L04N_0⁽³⁾
IO
IO
IO_L04P_0⁽³⁾
IO_L13N_0⁽³⁾
IO
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L05N_0
IO_L05P_0/VREF_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
FG676 Pin
Number
A3
A5
A6
C4
C8
C12
E13
H11
H12
B3
F7
G10
E5
D5
B4
A4
C5
B5
E6
D6
C6
B6
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
VREF
VREF
DCI
DCI
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
190