XC3S5000-5FGG676C Datasheet, PDF (42/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Table 22: Status Logic Signals
Signal
Direction
Description
RST
Input
A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay of zero.
Sets the LOCKED output Low. This input is asynchronous.
STATUS[7:0]
Output The bit values on the STATUS bus provide information regarding the state of DLL and PS operation
LOCKED
Output
Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals are
out-of-phase when Low.
Table 23: DCM STATUS Bus
Bit
Name
Description
A value of 1 indicates a phase shift overflow when one of two conditions occurs:
0 Phase Shift Overflow Incrementing (or decrementing) TPS beyond 255/256 of a CLKIN cycle.
The DLL is producing its maximum possible phase shift (i.e., all delay taps are active).⁽¹⁾
1
CLKIN Input Stopped A value of 1 indicates that the CLKIN input signal is not toggling. A value of 0 indicates toggling. This
Toggling
bit functions only when the CLKFB input is connected.⁽²⁾
2
CLKFX/CLKFX180
Output Stopped
Toggling
A value of 1 indicates that the CLKFX or CLKFX180 output signals are not toggling. A value of 0
indicates toggling. This bit functions only when using the Digital Frequency Synthesizer (DFS).
3:7 Reserved
–
Notes:
1. The DLL phase shift with all delay taps active is specified as the parameter FINE_SHIFT_RANGE.
2. If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit will not go High when the CLKIN signal stops.
Table 24: Status Attributes
Attribute
Description
STARTUP_WAIT Delays transition from configuration to user mode until lock condition is achieved.
Values
TRUE, FALSE
Stabilizing DCM Clocks Before User Mode
It is possible to delay the completion of device configuration until after the DLL has achieved a lock condition using the
STARTUP_WAIT attribute described in Table 24. This option ensures that the FPGA does not enter user mode—i.e., begin
functional operation—until all system clocks generated by the DCM are stable. In order to achieve the delay, it is necessary
to set the attribute to TRUE as well as set the BitGen option LCK_cycle to one of the six cycles making up the Startup phase
of configuration. The selected cycle defines the point at which configuration will halt until the LOCKED output goes High.
Global Clock Network
Spartan-3 devices have eight Global Clock inputs called GCLK0 - GCLK7. These inputs provide access to a
low-capacitance, low-skew network that is well-suited to carrying high-frequency signals. The Spartan-3 FPGAs clock
network is shown in Figure 23. GCLK0 through GCLK3 are located in the center of the bottom edge. GCLK4 through GCLK7
are located in the center of the top edge.
Eight Global Clock Multiplexers (also called BUFGMUX elements) are provided that accept signals from Global Clock inputs
and route them to the internal clock network as well as DCMs. Four BUFGMUX elements are located in the center of the
bottom edge, just above the GCLK0 - GCLK3 inputs. The remaining four BUFGMUX elements are located in the center of
the top edge, just below the GCLK4 - GCLK7 inputs.
Pairs of BUFGMUX elements share global inputs, as shown in Figure 24. For example, the GCLK4 and GCLK5 inputs both
potentially connect to BUFGMUX4 and BUFGMUX5 located in the upper right center. A differential clock input uses a pair of
GCLK inputs to connect to a single BUFGMUX element.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
42