XC3S5000-5FGG676C Datasheet, PDF (173/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 98: FG320 Package Pinout (Cont’d)
Bank
XC3S400, XC3S1000, XC3S1500
Pin Name
N/A VCCINT
N/A VCCINT
VCCAUX CCLK
VCCAUX DONE
VCCAUX HSWAP_EN
VCCAUX M0
VCCAUX M1
VCCAUX M2
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
VCCAUX TDO
VCCAUX TMS
FG320
Pin Number
N6
N7
T15
R15
E6
P5
U3
R4
E5
E14
D4
D15
B16
Type
VCCINT
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
User I/Os by Bank
Table 99 indicates how the available user-I/O pins are distributed between the eight I/O banks on the FG320 package.
Table 99: User I/Os Per Bank in FG320 Package
Package Edge
I/O Bank
Maximum Maximum
I/O
LVDS Pairs
I/O
0
26
11
19
Top
1
26
11
19
Right
2
29
14
23
3
29
14
23
Bottom
4
27
11
13
5
26
11
13
6
29
14
23
Left
7
29
14
23
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
2
3
0
2
3
0
2
4
0
2
4
6
2
4
6
2
3
0
2
4
0
2
4
GCLK
2
2
0
0
2
2
0
0
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
173