XC3S5000-5FGG676C Datasheet, PDF (266/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Note: The FG(G)1156 package is discontinued. See
http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm.
Table 111 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S4000 in the
FG1156 package. Similarly, Table 112 shows how the available user-I/O pins are distributed between the eight I/O banks for
the XC3S5000 in the FG1156 package.
Table 111: User I/Os Per Bank for XC3S4000 in FG1156 Package
Package Edge
I/O
Bank
Maximum I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
90
79
0
2
7
Top
1
90
79
0
2
7
2
88
80
0
2
6
Right
3
88
79
0
2
7
4
90
73
6
2
7
Bottom
5
90
73
6
2
7
6
88
79
0
2
7
Left
7
88
79
0
2
7
GCLK
2
2
0
0
2
2
0
0
Notes:
1. The FG1156 and FGG1156 packages are discontinued. See www.xilinx.com/support/documentation/spartan-3.htm#19600.
Table 112: User I/Os Per Bank for XC3S5000 in FG1156 Package
Package Edge
I/O
Bank
Maximum I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
100
89
0
2
7
Top
1
100
89
0
2
7
2
96
87
0
2
7
Right
3
96
87
0
2
7
4
100
83
6
2
7
Bottom
5
100
83
6
2
7
6
96
87
0
2
7
Left
7
96
87
0
2
7
GCLK
2
2
0
0
2
2
0
0
Notes:
1. The FG1156 and FGG1156 packages are discontinued. See www.xilinx.com/support/documentation/spartan-3.htm#19600.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
266