XC3S5000-5FGG676C Datasheet, PDF (145/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 92 indicates how the available user-I/O pins are distributed between the eight I/O banks on the TQ144 package.
Table 92: User I/Os Per Bank in TQ144 Package
Package Edge
Top
Right
Bottom
Left
I/O Bank Maximum I/O
I/O
0
10
5
1
9
4
2
14
10
3
15
11
4
11
0
5
9
0
6
14
10
7
15
11
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
2
1
0
2
1
0
2
2
0
2
2
6
2
1
6
0
1
0
2
2
0
2
2
GCLK
2
2
0
0
2
2
0
0
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
145