XC3S5000-5FGG676C Datasheet, PDF (100/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 37
PROG_B
(Input)
INIT_B
(Open-Drain)
CCLK
(Input/Output)
DIN
(Input)
DOUT
(Output)
T_CCL
T_CCH
T_DCC
T_CCD
Bit 0
Bit 1
1/F_CCSER
Bit n Bit n+1
T_CCO
Bit n-64 Bit n-63
Figure 37: Waveforms for Master and Slave Serial Configuration
DS099-3_04_071604
Table 66: Timing for the Master and Slave Serial Configuration Modes
Symbol
Description
Slave/
Master
Clock-to-Output Times
T_CCO
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
Setup Times
T_DCC
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
Hold Times
T_CCD
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
Clock Timing
T_CCH
T_CCL
F_CCSER
CCLK input pin High pulse width
CCLK input pin Low pulse width
Frequency of the clock signal at the
CCLK input pin
No bitstream compression
With bitstream compression
During STARTUP phase
ΔF_CCSER Variation from the CCLK output frequency set using the ConfigRate BitGen
option
Both
Both
Both
Slave
Master
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 32.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
All Speed Grades
Min
Max
Units
1.5
12.0
ns
10.0
–
ns
0
–
ns
5.0
5.0
0
0
0
–50%
∞
∞
66⁽²⁾
20
50
+50%
ns
ns
MHz
MHz
MHz
–
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
100