XC3S5000-5FGG676C Datasheet, PDF (55/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Initial Spartan-3 FPGA mask revisions have a limit on how fast the V_CCO supply can ramp. The minimum allowed V_CCO ramp
rate appears as T_CCO in Table 30, page 60. The minimum rate is affected by the package inductance. Consequently, the ball
grid array and chip-scale packages (CP132, FT256, FG456, FG676, and FG900) allow a faster ramp rate than the quad-flat
packages (VQ100, TQ144, and PQ208).
Configuration Data Retention, Brown-Out
The FPGA’s configuration data is stored in robust CMOS configuration latches. The data in these latches is retained even
when the voltages drop to the minimum levels necessary to preserve RAM contents. This is specified in Table 31, page 60.
If, after configuration, the V_CCAUX or V_CCINT supply drops below its data retention voltage, clear the current device
configuration using one of the following methods:
• Force the V_CCAUX or V_CCINT supply voltage below the minimum Power On Reset (POR) voltage threshold Table 29,
page 59).
• Assert PROG_B Low.
The POR circuit does not monitor the VCCO_4 supply after configuration. Consequently, dropping the VCCO_4 voltage
does not reset the device by triggering a Power-On Reset (POR) event.
No Internal Charge Pumps or Free-Running Oscillators
Some system applications are sensitive to sources of analog noise. Spartan-3 FPGA circuitry is fully static and does not
employ internal charge pumps.
The CCLK configuration clock is active during the FPGA configuration process. After configuration completes, the CCLK
oscillator is automatically disabled unless the Bitstream Generator (BitGen) option Persist=Yes. See Module 4: Table 80,
page 125.
Spartan-3 FPGAs optionally support a featured called Digitally Controlled Impedance (DCI). When used in an application,
the DCI logic uses an internal oscillator. The DCI logic is only enabled if the FPGA application specifies an I/O standard that
requires DCI (LVDCI_33, LVDCI_25, etc.). If DCI is not used, the associated internal oscillator is also disabled.
In summary, unless an application uses the Persist=Yes option or specifies a DCI I/O standard, an FPGA with no external
switching remains fully static.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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