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XC3S5000-5FGG676C Datasheet, PDF (81/272 Pages) Xilinx, Inc – Introduction and Ordering Information
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Spartan-3 FPGA Family: DC and Switching Characteristics
Timing Measurement Methodology
When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions.
Table 48 presents the conditions to use for each standard.
The method for measuring Input timing is as follows: A signal that swings between a Low logic level of VL and a High logic
level of VH is applied to the Input under test. Some standards also require the application of a bias voltage to the VREF pins
of a given bank to properly set the input-switching threshold. The measurement point of the Input signal (VM) is commonly
located halfway between VL and VH.
The Output test setup is shown in Figure 35. A termination voltage VT is applied to the termination resistor RT, the other end
of which is connected to the Output. For each standard, RT and VT generally take on the standard values recommended for
minimizing signal reflections. If the standard does not ordinarily use terminations (e.g., LVCMOS, LVTTL), then RT is set to
1MΩ to indicate an open connection, and VT is set to zero. The same measurement point (VM) that was used at the Input is
also used at the Output.
X-Ref Target - Figure 35
VT (VREF)
FPGA Output
RT (RREF)
VM (VMEAS)
CL (CREF)
ds099-3_07_012004
Notes:
1. The names shown in parentheses are
used in the IBIS file.
Figure 35: Output Test Setup
Table 48: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Single-Ended
GTL
GTL_DCI
GTLP
GTLP_DCI
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
HSTL_I
HSTL_I_DCI
HSTL_III
HSTL_III_DCI
HSTL_I_18
HSTL_I_DCI_18
HSTL_II_18
HSTL_II_DCI_18
VREF (V)
0.8
1.0
0.9
Inputs
VL (V)
VREF – 0.2
VREF – 0.2
VREF – 0.5
VH (V)
VREF + 0.2
VREF + 0.2
VREF + 0.5
0.75
0.90
0.90
0.90
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF – 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
Outputs
RT (Ω)
VT (V)
25
1.2
50
1.2
25
1.5
50
1.5
1M
0
50
0.75
50
1.5
50
0.9
50
0.9
Inputs and
Outputs
VM (V)
VREF
VREF
0.75
0.90
1.25
1.65
VREF
VREF
VREF
VREF
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
81
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