XC3S5000-5FGG676C Datasheet, PDF (40/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Table 20: PS Attributes
Attribute
CLKOUT_PHASE_SHIFT
PHASE_SHIFT
Description
Disables PS component or chooses between Fixed Phase and
Variable Phase modes.
Determines size and direction of initial fine phase shift.
Values
NONE, FIXED, VARIABLE
Integers from –255 to +255⁽¹⁾
Notes:
1. The practical range of values will be less when T_CLKIN > FINE_SHIFT_RANGE in the Fixed Phase mode, also when T_CLKIN >
(FINE_SHIFT_RANGE)/2 in the Variable Phase mode. the FINE_SHIFT_RANGE represents the sum total delay of all taps.
The Variable Phase Mode
The “Variable Phase” mode dynamically adjusts the fine phase shift over time using three inputs to the PS component,
namely PSEN, PSCLK and PSINCDEC, as defined in Table 21.
After device configuration, the PS component initially determines T_PS by evaluating Equation (4) for the value assigned to
the PHASE_SHIFT attribute. Then to dynamically adjust that phase shift, use the three PS inputs to increase or decrease
the fine phase shift.
PSINCDEC is synchronized to the PSCLK clock signal, which is enabled by asserting PSEN. It is possible to drive the
PSCLK input with the CLKIN signal or any other clock signal. A request for phase adjustment is entered as follows: For each
PSCLK cycle that PSINCDEC is High, the PS component adds 1/256 of a CLKIN cycle to T_PS. Similarly, for each enabled
PSCLK cycle that PSINCDEC is Low, the PS component subtracts 1/256 of a CLKIN cycle from T_PS. The phase adjustment
may require as many as 100 CLKIN cycles plus three PSCLK cycles to take effect, at which point the output PSDONE goes
High for one PSCLK cycle. This pulse indicates that the PS component has finished the present adjustment and is now
ready for the next request. Asserting the Reset (RST) input, returns T_PS to its original shift time, as determined by the
PHASE_SHIFT attribute value. The set of waveforms in section [c] of Figure 23, page 41 illustrates the relationship between
CLKFB and CLKIN in the Variable Phase mode.
Table 21: Signals for Variable Phase Mode
Signal
PSEN ⁽¹⁾
PSCLK ⁽¹⁾
Direction
Input
Input
Description
Enables PSCLK for variable phase adjustment.
Clock to synchronize phase shift adjustment.
PSINCDEC⁽¹⁾
Input
Chooses between increment and decrement for phase adjustment. It is synchronized to the PSCLK
signal.
PSDONE
Output
Goes High to indicate that present phase adjustment is complete and PS component is ready for next
phase adjustment request. It is synchronized to the PSCLK signal.
Notes:
1. It is possible to program this input for either a true or inverted polarity
DS099 (v3.1) June 27, 2013
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Product Specification
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