XC3S5000-5FGG676C Datasheet, PDF (75/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 45: Timing for the IOB Output Path
Symbol
Description
Conditions
Device
Clock-to-Output Times
T_IOCKP
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OTCLK input to
data appearing at the Output pin
LVCMOS25⁽²⁾, 12 mA output
drive, Fast slew rate
Propagation Times
T_IOOP
The time it takes for data to travel from LVCMOS25⁽²⁾, 12 mA output
the IOB’s O input to the Output pin drive, Fast slew rate
T_IOOLP
The time it takes for data to travel from
the O input through the OFF latch to
the Output pin
Set/Reset Times
T_IOSRP
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
LVCMOS25⁽²⁾, 12 mA output
drive, Fast slew rate
T_IOGSRQ
Time from asserting the Global Set
Reset (GSR) net to setting/resetting
data at the Output pin
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
Speed Grade
-5
-4
Max⁽³⁾ Max⁽³⁾
Units
1.28
1.47
ns
1.95
2.24
ns
1.28
1.46
ns
1.94
2.23
ns
1.28
1.47
ns
1.95
2.24
ns
2.10
2.41
ns
2.77
3.18
ns
8.07
9.28
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 48 and are based on the operating conditions set forth in
Table 32 and Table 35.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 47.
3. For minimums, use the values reported by the Xilinx timing analyzer.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
75