XC3S5000-5FGG676C Datasheet, PDF (52/272 Pages) Xilinx, Inc – Introduction and Ordering Information

X-Ref Target - Figure 30
Power-On
Spartan-3 FPGA Family: Functional Description
Set PROG_B Low
after Power-On
V_CCINT >1V
and V_CCAUX > 2V
No
and V_CCO Bank 4 > 1V
Yes
Clear
configuration
memory
No
INIT_B = High?
Yes
PROG_B = Low
No
Yes
Sample
mode pins
(JTAG port becomes
available)
Load CFG_IN
instruction
Load configuration
data frames
Shutdown
sequence
Load
JShutdown
instruction
CRC
correct?
No _{INIT_B goes Low.}
Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
No
Yes
Reconfigure?
DS099_27_041103
Figure 30: Boundary-Scan Configuration Flow Diagram
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
52