XC3S5000-5FGG676C Datasheet, PDF (16/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Table 9: Differential I/O Standards
Signal Standard
(IOSTANDARD)
LDT_25 (ULVDS_25)
LVDS_25
BLVDS_25
LVDSEXT_25
LVPECL_25
RSDS_25
DIFF_HSTL_II_18
DIFF_SSTL2_II
V_CCO (Volts)
For Outputs
2.5
2.5
2.5
2.5
2.5
2.5
1.8
2.5
Notes:
1. See Table 10 for a listing of the differential DCI standards.
For Inputs
–
–
–
–
–
–
–
–
V_REF for Inputs (Volts)
–
–
–
–
–
–
–
–
The need to supply V_REF and V_CCO imposes constraints on which standards can be used in the same bank. See The
Organization of IOBs into Banks section for additional guidelines concerning the use of the V_CCO and V_REF lines.
Digitally Controlled Impedance (DCI)
When the round-trip delay of an output signal—i.e., from output to input and back again—exceeds rise and fall times, it is
common practice to add termination resistors to the line carrying the signal. These resistors effectively match the impedance
of a device’s I/O to the characteristic impedance of the transmission line, thereby preventing reflections that adversely affect
signal integrity. However, with the high I/O counts supported by modern devices, adding resistors requires significantly more
components and board area. Furthermore, for some packages—e.g., ball grid arrays—it may not always be possible to
place resistors close to pins.
DCI answers these concerns by providing two kinds of on-chip terminations: Parallel terminations make use of an integrated
resistor network. Series terminations result from controlling the impedance of output drivers. DCI actively adjusts both
parallel and series terminations to accurately match the characteristic impedance of the transmission line. This adjustment
process compensates for differences in I/O impedance that can result from normal variation in the ambient temperature, the
supply voltage and the manufacturing process. When the output driver turns off, the series termination, by definition,
approaches a very high impedance; in contrast, parallel termination resistors remain at the targeted values.
DCI is available only for certain I/O standards, as listed in Table 10. DCI is selected by applying the appropriate I/O standard
extensions to symbols or components. There are five basic ways to configure terminations, as shown in Table 11. The DCI
I/O standard determines which of these terminations is put into effect.
HSTL_I_DCI-, HSTL_III_DCI-, and SSTL2_I_DCI-type outputs do not require the VRN and VRP reference resistors.
Likewise, LVDCI-type inputs do not require the VRN and VRP reference resistors. In a bank without any DCI I/O or a bank
containing non-DCI I/O and purely HSTL_I_DCI- or HSTL_III_DCI-type outputs, or SSTL2_I_DCI-type outputs or
LVDCI-type inputs, the associated VRN and VRP pins can be used as general-purpose I/O pins.
The HSLVDCI (High-Speed LVDCI) standard is intended for bidirectional use. The driver is identical to LVDCI, while the input
is identical to HSTL. By using a V_REF-referenced input, HSLVDCI allows greater input sensitivity at the receiver than when
using a single-ended LVCMOS-type receiver.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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