XC3S5000-5FGG676C Datasheet, PDF (132/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Table 87: VQ100 Package Pinout (Cont’d)
Bank
XC3S50
XC3S200
Pin Name
VQ100
Pin
Number
2
IO_L40N_2
P65
2
IO_L40P_2/VREF_2
P64
2
VCCO_2
P70
3
IO
P55
3
IO
P59
3
IO_L01N_3/VRP_3
P54
3
IO_L01P_3/VRN_3
P53
3
IO_L24N_3
P61
3
IO_L24P_3
P60
3
IO_L40N_3/VREF_3
P63
3
IO_L40P_3
P62
3
VCCO_3
P57
4
IO_L01N_4/VRP_4
P50
4
IO_L01P_4/VRN_4
P49
4
IO_L27N_4/DIN/D0
P48
4
IO_L27P_4/D1
P47
4
IO_L30N_4/D2
P44
4
IO_L30P_4/D3
P43
4
IO_L31N_4/INIT_B
P42
4
IO_L31P_4/DOUT/BUSY
P40
4
IO_L32N_4/GCLK1
P39
4
IO_L32P_4/GCLK0
P38
4
VCCO_4
P46
5
IO_L01N_5/RDWR_B
P28
5
IO_L01P_5/CS_B
P27
5
IO_L28N_5/D6
P32
5
IO_L28P_5/D7
P30
5
IO_L31N_5/D4
P35
5
IO_L31P_5/D5
P34
5
IO_L32N_5/GCLK3
P37
5
IO_L32P_5/GCLK2
P36
5
VCCO_5
P31
6
IO
P17
6
IO
P21
6
IO_L01N_6/VRP_6
P23
6
IO_L01P_6/VRN_6
P22
6
IO_L24N_6/VREF_6
P16
6
IO_L24P_6
P15
6
IO_L40N_6
P14
Type
I/O
VREF
VCCO
I/O
I/O
DCI
DCI
I/O
I/O
VREF
I/O
VCCO
DCI
DCI
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VCCO
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
GCLK
GCLK
VCCO
I/O
I/O
DCI
DCI
VREF
I/O
I/O
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
132