XC3S5000-5FGG676C Datasheet, PDF (147/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
PQ208: 208-lead Plastic Quad Flat Pack
The 208-lead plastic quad flat package, PQ208, supports three different Spartan-3 devices, including the XC3S50, the
XC3S200, and the XC3S400. The footprints for the XC3S200 and XC3S400 are identical, as shown in Table 93 and
Figure 47. The XC3S50, however, has fewer I/O pins resulting in 17 unconnected pins on the PQ208 package, labeled as
“N.C.” In Table 93 and Figure 47, these unconnected pins are indicated with a black diamond symbol ().
All the package pins appear in Table 93 and are sorted by bank number, then by pin name. Pairs of pins that form a
differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S50 pinout and the pinout for the XC3S200 and XC3S400, then that difference is
highlighted in Table 93. If the table entry is shaded grey, then there is an unconnected pin on the XC3S50 that maps to a
user-I/O pin on the XC3S200 and XC3S400. If the table entry is shaded tan, then the unconnected pin on the XC3S50 maps
to a VREF-type pin on the XC3S200 and XC3S400. If the other VREF pins in the bank all connect to a voltage reference to
support a special I/O standard, then also connect the N.C. pin on the XC3S50 to the same VREF voltage. This provides
maximum flexibility as you could potentially migrate a design from the XC3S50 device to an XC3S200 or XC3S400 FPGA
without changing the printed circuit board.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
http://www.xilinx.com/support/documentation/data_ sheets/s3_pin.zip
Pinout Table
Table 93: PQ208 Package Pinout
Bank
XC3S50
Pin Name
XC3S200, XC3S400
Pin Names
0
IO
IO
0
IO
0
N.C. ()
IO
IO/VREF_0
0
IO/VREF_0
IO/VREF_0
0
IO_L01N_0/VRP_0
IO_L01N_0/VRP_0
0
IO_L01P_0/VRN_0
IO_L01P_0/VRN_0
0
IO_L25N_0
IO_L25N_0
0
IO_L25P_0
IO_L25P_0
0
IO_L27N_0
IO_L27N_0
0
IO_L27P_0
IO_L27P_0
0
IO_L30N_0
IO_L30N_0
0
IO_L30P_0
IO_L30P_0
0
IO_L31N_0
IO_L31N_0
0
IO_L31P_0/VREF_0
IO_L31P_0/VREF_0
0
IO_L32N_0/GCLK7
IO_L32N_0/GCLK7
0
IO_L32P_0/GCLK6
IO_L32P_0/GCLK6
0
VCCO_0
VCCO_0
0
VCCO_0
VCCO_0
1
IO
IO
1
IO
IO
1
IO
IO
1
IO_L01N_1/VRP_1
IO_L01N_1/VRP_1
1
IO_L01P_1/VRN_1
IO_L01P_1/VRN_1
PQ208 Pin
Number
P189
P197
P200
P205
P204
P203
P199
P198
P196
P194
P191
P190
P187
P185
P184
P183
P188
P201
P167
P175
P182
P162
P161
Type
I/O
I/O
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
GCLK
GCLK
VCCO
VCCO
I/O
I/O
I/O
DCI
DCI
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
147