XC3S5000-5FGG676C Datasheet, PDF (67/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
X-Ref Target - Figure 33
Internal
Logic
V_OUTP
P
N
V_OUTN
Differential
I/O Pair Pins
V_OUTN
V_OUTP
GND level
50%
V_OCM
V_OD
V_OH
V_OL
V_OCM = Output common mode voltage =
V_OUTP + V_OUTN
2
V_OD = Output differential voltage = ^V_OUTP ^{- V}_OUTN
V_OH = Output voltage indicating a High logic level
V_OL ^{= Output voltage indicating a Low logic level} _{DS099-3_02_091710}
Figure 33: Differential Output Voltages
Table 38: DC Characteristics of User I/Os Using Differential Signal Standards
Signal Standard
LDT_25 (ULVDS_25)
Mask⁽³⁾
Revision
All
Min (mV)
430⁽⁴⁾
V_OD
Typ (mV)
600
Max (mV)
670
Min (V)
0.495
V_OCM
Typ (V)
0.600
Max (V)
0.715
V_OH
Min (V)
0.71
V_OL
Max (V)
0.50
LVDS_25
All
100
–
600
0.80
–
1.6
0.85
1.55
BLVDS_25⁽⁵⁾
‘E’
200
–
500
1.0
–
1.5
1.10
1.40
All
250
350
450
–
1.20
–
–
–
LVDSEXT_25
All
100
–
600
0.80
–
1.6
0.85
1.55
LVPECL_25⁽⁵⁾
RSDS_25⁽⁶⁾
‘E’
300
–
700
1.0
–
1.5
1.15
1.35
All
–
–
-
–
–
-
1.35
1.005
All
100
–
600
0.80
–
1.6
0.85
1.55
‘E’
200
–
500
1.0
–
1.5
1.10
1.40
DIFF_HSTL_II_18
All
–
–
–
–
–
–
V_CCO – 0.40
0.40
DIFF_SSTL2_II
All
–
–
–
–
–
–
V_TT + 0.80 V_TT – 0.80
Notes:
1. The numbers in this table are based on the conditions set forth in Table 32 and Table 37.
2. Output voltage measurements for all differential standards are made with a termination resistor (R_T) of 100Ω across the N and P pins of the
differential signal pair.
3. Mask revision E devices have tighter output ranges but can be used in any design that was in a previous revision. See Mask and Fab
Revisions, page 58.
4. This value must be compatible with the receiver to which the FPGA’s output pair is connected.
5. Each LVPECL_25 or BLVDS_25 output-pair requires three external resistors for proper output operation as shown in Figure 34. Each
LVPECL_25 or BLVDS_25 input-pair uses a 100W termination resistor at the receiver.
6. Only one of the differential standards RSDS_25, LDT_25, LVDS_25, and LVDSEXT_25 may be used for outputs within a bank.
Each differential standard input-pair requires an external 100Ω termination resistor.
X-Ref Target - Figure 34
LVPECL _70Ω
Z0=50Ω
240Ω
LVPECL
100Ω
BLVDS _165Ω
Z0=50Ω
140Ω
BLVDS
100Ω
Z0=50Ω
70Ω
165Ω
Z0=50Ω
ds099-3_08_112105
Figure 34: External Termination Required for LVPECL and BLVDS Output and Input
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
67