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| XC3S5000-5FGG676C Datasheet, PDF (61/272 Pages) Xilinx, Inc – Introduction and Ordering Information | |||
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 33: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
Description
Test Conditions
Min Typ Max Units
IL(2)(4)
Leakage current at User I/O,
Dual-Purpose, and Dedicated pins
Driver is Hi-Z, VIN = VCCO ⥠3.0V
â
0V or VCCO max,
sample-tested
VCCO < 3.0V
â
-
±25
μA
-
±10
μA
IRPU(3)
Current through pull-up resistor at User I/O,
Dual-Purpose, and Dedicated pins
VIN = 0V, VCCO = 3.3V
VIN = 0V, VCCO = 3.0V
â0.84
-
â2.35 mA
â0.69
-
â1.99 mA
VIN = 0V, VCCO = 2.5V
â0.47
-
â1.41 mA
VIN = 0V, VCCO = 1.8V
â0.21
-
â0.69 mA
VIN = 0V, VCCO = 1.5V
â0.13
-
â0.43 mA
RPU(3)
Equivalent resistance of pull-up resistor at
User I/O, Dual-Purpose, and Dedicated
pins, derived from IRPU
VIN = 0V, VCCO = 1.2V
VCCO = 3.0V to 3.465V
VCCO = 2.3V to 2.7V
VCCO = 1.7V to 1.9V
â0.06
-
â0.22 mA
1.27
-
4.11
kΩ
1.15
-
3.25
kΩ
2.45
-
9.10
kΩ
VCCO = 1.4V to 1.6V
3.25
-
12.10
kΩ
IRPD(3)
Current through pull-down resistor at User
I/O, Dual-Purpose, and Dedicated pins
VCCO = 1.14 to 1.26V
VIN = VCCO
5.15
-
21.00
kΩ
0.37
-
1.67
mA
RPD(3)
Equivalent resistance of pull-down resistor
at User I/O, Dual-Purpose, and Dedicated
pins, driven from IRPD
VIN = VCCO = 3.0V to 3.465V
VIN = VCCO = 2.3V to 2.7V
VIN = VCCO = 1.7V to 1.9V
1.75
-
9.35
kΩ
1.35
-
7.30
kΩ
1.00
-
5.15
kΩ
VIN = VCCO = 1.4V to 1.6V
0.85
-
4.35
kΩ
RDCI
IREF
VIN = VCCO = 1.14 to 1.26V
Value of external reference resistor to support DCI I/O standards
VREF current per pin
VCCO ⥠3.0V
VCCO < 3.0V
0.68
-
3.465
kΩ
20
-
100
Ω
â
-
±25
μA
â
-
±10
μA
CIN
Input capacitance
3
-
10
pF
Notes:
1. The numbers in this table are based on the conditions set forth in Table 32.
2. The IL specification applies to every I/O pin throughout power-on as long as the voltage on that pin stays between the absolute VIN minimum
and maximum values (Table 28). For hot-swap applications, at the time of card connection, be sure to keep all I/O voltages within this range
before applying VCCO power. Consider applying VCCO power before connecting the signal lines, to avoid turning on the ESD protection
diodes, shown in Module 2: Figure 7, page 11. When the FPGA is completely unpowered, the I/O pins are high impedance, but there is a
path through the upper and lower ESD protection diodes.
3. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.
Spartan-3 family values for both resistances are stronger than they have been for previous FPGA families.
4. For single-ended signals that are placed on a differential-capable I/O, VIN of â0.2V to â0.3V is supported but can cause increased leakage
between the two pins. See the Parasitic Leakage section in UG331, Spartan-3 Generation FPGA User Guide.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
61
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