XC3S5000-5FGG676C Datasheet, PDF (139/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 89: CP132 Package Pinout (Cont’d)
Bank
XC3S50 Pin Name
CP132
Ball
Type
N/A GND
M3
GND
N/A GND
M13
GND
N/A GND
N6
GND
N/A GND
N11
GND
N/A VCCAUX
A5 VCCAUX
N/A VCCAUX
C10 VCCAUX
N/A VCCAUX
M5 VCCAUX
N/A VCCAUX
P10 VCCAUX
N/A VCCINT
B10 VCCINT
N/A VCCINT
C6 VCCINT
N/A VCCINT
M9 VCCINT
N/A VCCINT
N5 VCCINT
VCCAUX CCLK
P14 CONFIG
VCCAUX DONE
P13 CONFIG
VCCAUX HSWAP_EN
B3 CONFIG
VCCAUX M0
N1 CONFIG
VCCAUX M1
M2 CONFIG
VCCAUX M2
P1 CONFIG
VCCAUX PROG_B
A2 CONFIG
VCCAUX TCK
B14
JTAG
VCCAUX TDI
A1
JTAG
VCCAUX TDO
C13
JTAG
VCCAUX TMS
A14
JTAG
User I/Os by Bank
Table 90 indicates how the 89 available user-I/O pins are distributed between the eight I/O banks on the CP132 package.
There are only four output banks, each with its own VCCO voltage input.
Table 90: User I/Os Per Bank for XC3S50 in CP132 Package
Package Edge
I/O Bank Maximum I/O
I/O
0
10
5
Top
1
10
5
Right
2
12
8
3
12
8
4
11
0
Bottom
5
10
1
6
12
8
Left
7
12
9
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
2
1
0
2
1
0
2
2
0
2
2
6
2
1
6
0
1
0
2
2
0
2
1
GCLK
2
2
0
0
2
2
0
0
Notes:
1. The CP132 and CPG132 packages are discontinued. See www.xilinx.com/support/documentation/spartan-3.htm#19600.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
139