XC3S5000-5FGG676C Datasheet, PDF (123/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
Table 79: Pin Behavior After Power-Up, During Configuration (Cont’d)
Pin Name
Configuration Mode Settings <M2:M1:M0>
Serial Modes
SelectMap Parallel Modes
Master <0:0:0> Slave <1:1:1> Master <0:1:1> Slave <1:1:0>
JTAG Mode
<1:0:1>
Bitstream
Configuration
Option
IO_Lxxy_#/
D5
D5 (I/O)
D5 (I/O)
Persist UnusedPin
IO_Lxxy_#/
D6
D6 (I/O)
D6 (I/O)
Persist UnusedPin
IO_Lxxy_#/
D7
D7 (I/O)
D7 (I/O)
Persist UnusedPin
IO_Lxxy_#/
CS_B
CS_B (I)
CS_B (I)
Persist UnusedPin
IO_Lxxy_#/
RDWR_B
RDWR_B (I)
RDWR_B (I)
Persist UnusedPin
IO_Lxxy_#/
BUSY/DOUT
DOUT (O)
DOUT (O)
BUSY (O)
BUSY (O)
Persist UnusedPin
DUAL: Dual-purpose configuration pins (INIT_B has a pull-up resistor to VCCO_4 or VCCO_BOTTOM always active during
configuration, regardless of HSWAP_EN pin)
IO_Lxxy_#/
INIT_B
INIT_B (I/OD) INIT_B (I/OD) INIT_B (I/OD) INIT_B (I/OD)
UnusedPin
DCI: Digitally Controlled Impedance reference resistor input pins
IO_Lxxy_#/
VRN_#
UnusedPin
IO/VRN_#
UnusedPin
IO_Lxxy_#/
VRP_#
UnusedPin
IO/VRP_#
UnusedPin
GCLK: Global clock buffer inputs
IO_Lxxy_#/
GCLK0 through
GCLK7
UnusedPin
VREF: I/O bank input reference voltage pins
IO_Lxxy_#/
VREF_#
UnusedPin
IO/VREF_#
UnusedPin
CONFIG: Dedicated configuration pins (pull-up resistor to VCCAUX always active during configuration, regardless of
HSWAP_EN pin)
CCLK
CCLK (I/O)
CCLK (I)
CCLK (I/O)
CCLK (I)
CclkPin ConfigRate
PROG_B
PROG_B (I)
(pull-up)
PROG_B (I)
(pull-up)
PROG_B (I)
(pull-up)
PROG_B (I)
(pull-up)
PROG_B (I), Via
JPROG_B
instruction
ProgPin
DONE
DONE (I/OD)
DONE (I/OD)
DONE (I/OD)
DONE (I/OD)
DONE (I/OD)
DriveDone
DonePin DonePipe
M2
M2=0 (I)
M2=1 (I)
M2=0 (I)
M2=1 (I)
M2=1 (I)
M2Pin
M1
M1=0 (I)
M1=1 (I)
M1=1 (I)
M1=1 (I)
M1=0 (I)
M1Pin
M0
M0=0 (I)
M0=1 (I)
M0=1 (I)
M0=0 (I)
M0=1 (I)
M0Pin
HSWAP_EN
HSWAP_EN (I) HSWAP_EN (I) HSWAP_EN (I) HSWAP_EN (I) HSWAP_EN (I)
HswapenPin
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
123