XC3S5000-5FGG676C Datasheet, PDF (32/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
• Phase Shifting: The DCM provides the ability to shift the phase of all its output clock signals with respect to its input
clock signal.
The DCM has four functional components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), the
Phase Shifter (PS), and the Status Logic. Each component has its associated signals, as shown in Figure 19.
X-Ref Target - Figure 19
PSINCDEC
PSEN
PSCLK
DCM
Phase
Shifter
PSDONE
CLKIN
CLKFB
RST
DLL
Status
Logic
DFS
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
8
STATUS [7:0]
Clock
Distribution
Delay
DS099-2_07_040103
Figure 19: DCM Functional Blocks and Associated Signals
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to eliminate clock skew. The main signal path of the DLL consists of an
input stage, followed by a series of discrete delay elements or taps, which in turn leads to an output stage. This path together
with logic for phase detection and control forms a system complete with feedback as shown in Figure 20.
X-Ref Target - Figure 20
CLKIN
Delay
1
Delay
2
Delay
n-1
Delay
n
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Control
LOCKED
CLKFB
RST
Phase
Detection
DS099-2_08_041103
Figure 20: Simplified Functional Diagram of DLL
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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