XC3S5000-5FGG676C Datasheet, PDF (30/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 16
CLK
WE
DI
ADDR
DO
0000
XXXX
1111
2222
XXXX
aa
bb
cc
dd
MEM(aa)
old MEM(bb)
old MEM(cc)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS099-2_15_030403
Figure 16: Waveforms of Block RAM Data Operations with READ_FIRST Selected
Choosing a third attribute called NO_CHANGE puts the DO outputs in a latched state when asserting WE. Under this
condition, the DO outputs will retain the data driven just before WE was asserted. NO_CHANGE timing is shown in the
portion of Figure 17 during which WE is High.
X-Ref Target - Figure 17
CLK
WE
DI
XXXX
1111
2222
XXXX
ADDR
aa
bb
cc
dd
DO
0000
MEM(aa)
MEM(dd)
EN
DISABLED
READ
WRITE
MEM(bb)=1111
WRITE
MEM(cc)=2222
READ
DS099-2_16_030403
Figure 17: Waveforms of Block RAM Data Operations with NO_CHANGE Selected
Dedicated Multipliers
All Spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to produce a 36-bit product. This
section provides an introduction to multipliers. For further details, refer to the chapter entitled “Using Embedded Multipliers”
in UG331.
The input buses to the multiplier accept data in two’s-complement form (either 18-bit signed or 17-bit unsigned). One such
multiplier is matched to each block RAM on the die. The close physical proximity of the two ensures efficient data handling.
Cascading multipliers permits multiplicands more than three in number as well as wider than 18-bits. The multiplier is placed
in a design using one of two primitives: an asynchronous version called MULT18X18 and a version with a register called
MULT18X18S, as shown in Figure 18. The signals for these primitives are defined in Table 15.
The CORE Generator system produces multipliers based on these primitives that can be configured to suit a wide range of
requirements.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
30