XC3S5000-5FGG676C Datasheet, PDF (88/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 50: Recommended Number of Simultaneously Switching Outputs per V_CCO /GND Pair (Cont’d)
Signal Standard
(IOSTANDARD)
VQ100
TQ144
Package
PQ208
CP132
FT256, FG320, FG456,
FG676, FG900, FG1156
PCI33_3
9
9
9
9
9
SSTL18_I
13
13
13
13
17
SSTL18_I_DCI
13
13
13
13
17
SSTL18_II
8
8
8
8
9
SSTL2_I
10
10
10
10
13
SSTL2_I_DCI
10
10
10
10
13
SSTL2_II
6
6
6
6
9
SSTL2_II_DCI
6
6
6
6
9
Differential Standards (Number of I/O Pairs or Channels)
LDT_25 (ULVDS_25)
5
5
5
5
5
LVDS_25
7
5
5
12
20
BLVDS_25
2
1
1
4
LVDSEXT_25
5
5
5
5
5
LVPECL_25
2
1
1
4
RSDS_25
7
5
5
12
20
DIFF_HSTL_II_18
4
4
4
4
4
DIFF_HSTL_II_18_DCI
4
4
4
4
4
DIFF_SSTL2_II
3
3
3
3
4
DIFF_SSTL2_II_DCI
3
3
3
3
4
Notes:
1. The numbers in this table are recommendations that assume the FPGA is soldered on a printed circuit board using sound practices. This
table assumes the following parasitic factors: combined PCB trace and land inductance per V_CCO and GND pin of 1.0 nH, receiver capacitive
load of 15 pF. Test limits are the V_IL/V_IH voltage limits for the respective I/O standard.
2. Regarding the SSO numbers for all DCI standards, the R_REF resistors connected to the VRN and VRP pins of the FPGA are 50W..
3. If more than one signal standard is assigned to the I/Os of a given bank, refer to XAPP689: Managing Ground Bounce in Large FPGAs for
information on how to perform weighted average SSO calculations.
4. Results are based on actual silicon testing using an FPGA soldered on a typical printed-circuit board.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
88