XC3S5000-5FGG676C Datasheet, PDF (41/272 Pages) Xilinx, Inc – Introduction and Ordering Information

X-Ref Target - Figure 23
a. CLKOUT_PHASE_SHIFT = NONE
CLKIN
CLKFB
Spartan-3 FPGA Family: Functional Description
b. CLKOUT_PHASE_SHIFT = FIXED
CLKIN
Shift Range over all P Values:
–255
CLKFB
0
P
256 ^{* TCLKIN}
+255
c. CLKOUT_PHASE_SHIFT = VARIABLE
CLKIN
Shift Range over all P Values:
–255
CLKFB before
Decrement
Shift Range over all N Values:
CLKFB after
Decrement
0
P
256
*
T_CLKIN
+255
–255
0
N
256
*
T_CLKIN
+255
Notes:
DS099-2_11_031303
1. P represents the integer value ranging from –255 to +255 to which the PHASE_SHIFT attribute is assigned.
2. N is an integer value ranging from –255 to +255 that represents the net phase shift effect from a series of increment
and/or decrement operations.
N = {Total number of increments} – {Total number of decrements}
A positive value for N indicates a net increment; a negative value indicates a net decrement.
Figure 23: Phase Shifter Waveforms
The Status Logic Component
The Status Logic component not only reports on the state of the DCM but also provides a means of resetting the DCM to an
initial known state. The signals associated with the Status Logic component are described in Table 22.
As a rule, the Reset (RST) input is asserted only upon configuring the device or changing the CLKIN frequency. A DCM reset
does not affect attribute values (e.g., CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, RST must be tied to GND.
The eight bits of the STATUS bus are defined in Table 23.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
41