XC3S5000-5FGG676C Datasheet, PDF (26/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Functional Description
Arrangement of RAM Blocks on Die
The XC3S50 has one column of block RAM. The Spartan-3 devices ranging from the XC3S200 to XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000 have four columns. The position of the columns on the die is shown
in Figure 1, page 3. For a given device, the total available RAM blocks are distributed equally among the columns. Table 12
shows the number of RAM blocks, the data storage capacity, and the number of columns for each device.
Table 12: Number of RAM Blocks by Device
Device
Total Number Total Addressable Number of
of RAM Blocks Locations (Bits) Columns
XC3S50
4
73,728
1
XC3S200
12
221,184
2
XC3S400
16
294,912
2
XC3S1000
24
442,368
2
XC3S1500
32
589,824
2
XC3S2000
40
737,280
2
XC3S4000
96
1,769,472
4
XC3S5000
104
1,916,928
4
Block RAM and multipliers have interconnects between them that permit simultaneous operation; however, since the
multiplier shares inputs with the upper data bits of block RAM, the maximum data path width of the block RAM is 18 bits in
this case.
The Internal Structure of the Block RAM
The block RAM has a dual port structure. The two identical data ports called A and B permit independent access to the
common RAM block, which has a maximum capacity of 18,432 bits—or 16,384 bits when no parity lines are used. Each port
has its own dedicated set of data, control and clock lines for synchronous read and write operations. There are four basic
data paths, as shown in Figure 13: (1) write to and read from Port A, (2) write to and read from Port B, (3) data transfer from
Port A to Port B, and (4) data transfer from Port B to Port A.
X-Ref Target - Figure 13
Write
4 Read
Write
1
Read
Spartan-3
Dual Port
Block RAM
Read 3
Write
Write
2
Read
DS099-2_12_030703
Figure 13: Block RAM Data Paths
Block RAM Port Signal Definitions
Representations of the dual-port primitive RAMB16_S[w_A]_S[w_B] and the single-port primitive RAMB16_S[w] with their
associated signals are shown in Figure 14. These signals are defined in Table 13.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
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