XC3S5000-5FGG676C Datasheet, PDF (163/272 Pages) Xilinx, Inc – Introduction and Ordering Information

Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 97 indicates how the available user-I/O pins are distributed between the eight I/O banks on the FT256 package.
Table 97: User I/Os Per Bank in FT256 Package
Package Edge
I/O Bank Maximum I/O
I/O
0
20
13
Top
1
20
13
Right
2
23
18
3
23
18
4
21
8
Bottom
5
20
7
6
23
18
Left
7
23
18
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
2
3
0
2
3
0
2
3
0
2
3
6
2
3
6
2
3
0
2
3
0
2
3
GCLK
2
2
0
0
2
2
0
0
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
163