XC3S5000-5FGG676C Datasheet, PDF (135/272 Pages) Xilinx, Inc – Introduction and Ordering Information

VQ100 Footprint
X-Ref Target - Figure 44
Spartan-3 FPGA Family: Pinout Descriptions
IO_L01P_7/VRN_7 1
IO_L01N_7/VRP_7 2
GND 3
IO_L21P_7 4
IO_L21N_7 5
VCCO_7 6
VCCAUX 7
IO_L23P_7 8
IO_L23N_7 9
GND 10
IO_L40P_7 11
IO_L40N_7/VREF_7 12
IO_L40P_6/VREF_6 13
IO_L40N_6 14
IO_L24P_6 15
IO_L24N_6/VREF_6 16
IO 17
VCCINT 18
VCCO_6 19
GND 20
IO 21
IO_L01P_6/VRN_6 22
IO_L01N_6/VRP_6 23
M1 24
M0 25
Bank 0
Bank 5
(no VREF, no DCI)
Bank 1
Bank 4
(no VREF)
75 IO_L01N_2/VRP_2
74 IO_L01P_2/VRN_2
73 GND
72 IO_L21N_2
71 IO_L21P_2
70 VCCO_2
69 VCCINT
68 IO_L24N_2
67 IO_L24P_2
66 GND
65 IO_L40N_2
64 IO_L40P_2/VREF_2
63 IO_L40N_3/VREF_3
62 IO_L40P_3
61 IO_L24N_3
60 IO_L24P_3
59 IO
58 VCCAUX
57 VCCO_3
56 GND
55 IO
54 IO_L01N_3/VRP_3
53 IO_L01P_3/VRN_3
52 CCLK
51 DONE
DS099-4_15_042303
Figure 44: VQ100 Package Footprint (Top View). Note pin 1 indicator in top-left corner and logo orientation.
22 I/O: Unrestricted, general-purpose user I/O
14
DCI: User I/O or reference resistor input for
bank
7 CONFIG: Dedicated configuration pins
12
DUAL: Configuration pin, then possible
user I/O
8
GCLK: User I/O or global clock buffer
input
7
VREF: User I/O or input voltage reference for
bank
8 VCCO: Output voltage supply for bank
4 JTAG: Dedicated JTAG port pins
4 VCCINT: Internal core voltage supply (+1.2V)
0 N.C.: No unconnected pins in this package 10 GND: Ground
4 VCCAUX: Auxiliary voltage supply (+2.5V)
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
135