XC3S5000-5FGG676C Datasheet, PDF (37/272 Pages) Xilinx, Inc – Introduction and Ordering Information

X-Ref Target - Figure 22
Spartan-3 FPGA Family: Functional Description
Phase:
0^o 90^o 180^o 270^o 0^o 90^o 180^o 270^o 0^o
Input Signal (40% Duty Cycle)
t
CLKIN
Output Signal - Duty Cycle is Always Corrected
CLK2X
CLK2X180
CLKDV⁽¹⁾
Output Signal - Attribute Corrects Duty Cycle
DUTY_CYCLE_CORRECTION = FALSE
CLK0
CLK90
CLK180
CLK270
DUTY_CYCLE_CORRECTION = TRUE
CLK0
CLK90
CLK180
CLK270
DS099-2_10_051907
Figure 22: Characteristics of the DLL Clock Outputs
Digital Frequency Synthesizer (DFS)
The DFS component generates clock signals the frequency of which is a product of the clock frequency at the CLKIN input
and a ratio of two user-determined integers. Because of the wide range of possible output frequencies such a ratio permits,
the DFS feature provides still further flexibility than the DLL’s basic synthesis options as described in the preceding section.
The DFS component’s two dedicated outputs, CLKFX and CLKFX180, are defined in Table 19.
The signal at the CLKFX180 output is essentially an inversion of the CLKFX signal. These two outputs always exhibit a 50%
duty cycle. This is true even when the CLKIN signal does not. These DFS clock outputs are driven at the same time as the
DLL’s seven clock outputs.
The numerator of the ratio is the integer value assigned to the attribute CLKFX_MULTIPLY and the denominator is the
integer value assigned to the attribute CLKFX_DIVIDE. These attributes are described in Table 18.
DS099 (v3.1) June 27, 2013
www.xilinx.com
Product Specification
37